SkillGen: Automated Demonstration Generation for Efficient Skill Learning and Deployment

Guan-Ting (Danny) Liu

Guan-Ting (Danny) Liu completed his Ph.D. in the Graduate Institute of Networking and Multimedia at National Taiwan University in Taipei, Taiwan. During his Ph.D. program, he is advised by Pu-Jen Cheng, Iris Hui-Ru Jiang, and Shao-Hua Sun.

Prithvijit Chattopadhyay

I am a Research Scientist in Deep Imagination Research. I earned my Ph.D. in Computer Science in August 2024 at Georgia Tech, where I was advised by Prof. Judy Hoffman. During my Ph.D., I broadly worked on distribution shift problems in computer vision. My doctoral thesis (see here) was focused on utilizing synthetic data to train robust and reliable vision models.

Avnish Narayan

Drew Zagieboylo

Drew joined NVIDIA's Security and Privacy research team in the summer of 2024 after having received his PhD in Computer Science from Cornell University in 2023. His research focuses on applying programming language design, tools, and techniques to security problems across the hardware—software stack. In particular, he is interested in enabling engineers and designers to build resilient systems whose confidentiality and integrity can be trusted and measured.

Yejin Choi

Yejin Choi is a distinguished scientist of Language and Cognition Research at NVIDIA. Her current research focuses on large language models, large reasoning models, and alternative architectures. She is a MacArthur Fellow (class of 2022), named among Time100 Most Influential People in AI in 2023, and a co-recipient of 2 Test-of-Time awards (ACL 2021 and CVPR 2021) and 8 Best and Outstanding Paper Awards at ACL, EMNLP, NAACL, ICML, NeurIPS, and AAAI.

Kris Wu

Kris Wu is a Research Scientist at NVIDIA Research, where he focuses on efficient decision-making and optimization with LLMs. He obtained his PhD in Computer Science from the University of California, San Diego, under the supervision of Prof. Xiaolong Wang. Before joining NVIDIA, he was a student researcher at Google DeepMind.

LLM Pruning and Distillation in Practice: The Minitron Approach

VerilogCoder: Autonomous Verilog Coding Agents with Graph-based Planning and Abstract Syntax Tree (AST)-based Waveform Tracing Tool

Due to the growing complexity of modern Integrated Circuits (ICs), automating hardware design can prevent a significant amount of human error from the engineering process and result in less errors. Verilog is a popular hardware description language for designing and modeling digital systems; thus, Verilog generation is one of the emerging areas of research to facilitate the design process.

Large Language Model (LLM) for Standard Cell Layout Design Optimization

Standard cells are essential components of modern digital circuit designs. With process technologies advancing toward 2nm, more routability issues have arisen due to the decreasing number of routing tracks, increasing number and complexity of design rules, and strict patterning rules. The state-of-the-art standard cell design automation framework is able to automatically design standard cell layouts in advanced nodes, but it is still struggling to generate highly competitive Performance-Power-Area (PPA) and routable cell layouts for complex sequential cell designs.

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