Harini joined NVIDIA in February 2022 as a part of the System Architecture Research Group. Her research focuses on developing GPU and interconnect solutions for scalable multi-GPU systems.
Fine-grained peer-to-peer stores as a communication paradigm has the potential to improve strong scaling, but existing GPU and interconnect architectures are unable to benefit from such transfers due to several limitations. One such limitation is the poor interconnect efficiency of small peer-to-peer stores. Small stores arise naturally in multi-GPU programming models based on a single address space shared across all devices, but they do not map well onto current inter-GPU interconnects, which remain optimized for bulk transfers rather than small (4-32B) operations. Her present work explores GPU HW enhancements to address this challenge while remaining transparent to the programmer.
Prior to joining NVIDIA, Harini was a Ph.D. candidate at the Univeristy of Michigan, where she was advised by Prof. Thomas Wenisch.
