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  2. A 28nm 2Mbit 6T SRAM with Highly Configurable Write Assist Implementation and Capacitor Based Sense Amplifier Input Offset Compen

A 28nm 2Mbit 6T SRAM with Highly Configurable Write Assist Implementation and Capacitor Based Sense Amplifier Input Offset Compen

Authors

Mahmut Sinangil (NVIDIA)
John Poulton (NVIDIA)
Matt Fojtik
Trey Greer
Stephen Tell
Andy Gotterba (NVIDIA)
Jesse Wang (NVIDIA)
Jason Golbus (NVIDIA)
William Dally
Tom Gray

Publication Date

Published in

Journal of Solid State Circuits

Research Area

Circuits and VLSI Design

Copyright

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