Standard cell layouts in advanced technology nodes are done manually in the industry today. Automating standard cell layouts is challenging because of the exploding number and complexity of design rule checking (DRC), especially when the design goal is to minimize cell area. In this paper we propose a machine learning based approach to handle DRC constrains. In our approach, we apply a genetic algorithm to create routing candidates and use reinforcement learning (RL) to fix the design rule violations incrementally. A design rule checker provides feedback on violations to the RL agent and the agent learns how to fix them based on the data. This approach is also applicable to future technologies with unseen DRCs. Based on this approach, we built a layout generator called NVCell that includes a device placer based on a simulated annealing method and a router based on a genetic algorithm and reinforcement learning. NVCell can generate layouts with equal or smaller area for over 75% of cells in an industry standard cell library.