Dr. Aamer Jaleel joined NVIDIA in 2015 and is a member of the Architecture Research Group (ARG). His research work focuses on cache and DRAM systems, workload scheduling, performance modeling, and workload characterization. Prior to joining NVIDIA, he was a Principal Engineer at Intel Massachusetts Inc. in the VSSAD research group. During his decade-long career at Intel, his research work contributed towards enhancement in performance modeling and cache hierarchy improvements of Intel’s next generation microprocessors. In the Fall of 2014, during his extended sabbatical from Intel, he also served as a Visiting Professor at the University of Minnesota, Minneapolis-St. Paul where he co-taught a graduate computer architecture course.
Jaleel received his Ph.D. in Electrical Engineering from the University of Maryland, College Park in 2006. He received his B.S. and M.S. in Computer Engineering also from the University of Maryland, College Park in 2000 and 2002 respectively. Jaleel has co-authored more than a dozen patents and over 30 technical publications.