Joel Emer

Dr. Joel S. Emer joined NVIDIA in 2014 and is a member of the Architecture Research group. He is also a Professor of the Practice at MIT. He is responsible for exploration of future architectures as well as modeling and analysis methodologies. Prior to joining NVIDIA he worked at Intel where he was an Intel Fellow and Director of Microarchitecture Research.  Previously he worked at Compaq and Digital Equipment Corporation.

Emer has held various research and advanced development positions investigating processor microarchitecture and developing performance modeling and evaluation techniques. He has made architectural contributions to a number of VAX, Alpha and X86 processors and is recognized as one of the developers of the widely employed quantitative approach to processor performance evaluation. More recently, he has been recognized for his contributions in the advancement of simultaneous multithreading technology, processor reliability analysis, cache organization and spatial architectures.

Emer received a bachelor's degree with highest honors in electrical engineering in 1974, and his master's degree in 1975 -- both from Purdue University. He earned a doctorate in electrical engineering from the University of Illinois in 1979. Emer has received numerous public recognitions, including being named a Fellow of both the ACM and IEEE, and he was the 2009 recipient of the Eckert-Mauchly award for lifetime contributions in computer architecture.