Publications

Our publications provide insight into some of our leading-edge research.

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2018

A Case for Richer Cross-layer Abstractions: Bridging the Semantic Gap to Enhance Memory Optimization
Nandita Vijaykumar, Abhilasha Jain, Diptesh Majumdar, Kevin Hsieh, Gennady Pekhimenko, Eiman Ebrahimi, Nastaran Hajinazar, Phillip B. Gibbons, Onur Mutlu
The Locality Descriptor: A Holistic Cross-Layer Abstraction to Express Data Locality in GPUs
Nandita Vijayumar, Eiman Ebrahimi, Kevin Hsieh, Phillip B. Gibbons, Onur Mutlu
UCNN: Exploiting Computational Reuse in Deep Neural Networks via Weight Repetition
Kartik Hegde, Jiyong Yu, Rohit Agrawal, Mengjia Yan, Michael Pellauer, Christopher W. Fletcher
ACCORD: Enabling Associativity for Gigascale DRAM Caches by Coordinating Way-Install and Way-Prediction
Vinson Young, Chiachen Chou, Aamer Jaleel, Moinuddin Qureshi
Full-Stack Memory Model Verification with TriCheck
Caroline Trippel, Yatin A. Manerkar, Daniel Lustig, Michael Pellauer, Margaret Martonosi
Voltron: Understanding and Exploiting the Voltage-Latency-Reliability Trade-Offs in Modern DRAM Chips to Improve Energy Efficiency
Kevin K. Chang, Abdullah Giray Yağlıkçı, Saugata Ghose, Aditya Agrawal, Niladrish Chatterjee, Abhijith Kashyap, Donghyuk Lee, Mike O'Connor, Hasan Hassan, Onur Mutlu
DUO: Exposing On-chip Redundancy to Rank-Level ECC for High Reliability
Seong-Lyong Gong, Jungrae Kim, Michael B. Sullivan, Howard David, Mattan Erez
Compressing DMA Engine: Leveraging Activation Sparsity for Training Deep Neural Networks
Minsoo Rhu, Mike O'Connor, Niladrish Chatterjee, Jeff Pool, Youngeun Kwon, Steve Keckler
Reducing Data Transfer Energy by Exploiting Similarity within a Data Transaction
Donghyuk Lee, Mike O'Connor, Niladrish Chatterjee
Best Paper nominee
Stitch-X: An Accelerator Architecture for Exploiting Unstructured Sparsity in Deep Neural Networks
Ching-En Lee, Yakun Sophia Shao, Jie-Fang Zhang, Angshuman Parashar, Joel Emer, Steve Keckler, Zhengya Zhang
MeltdownPrime and SpectrePrime: Automatically-Synthesized Attacks Exploiting Invalidation-Based Coherence Protocols
Caroline Trippel, Daniel Lustig, Margaret Martonosi

2017

Toward Standardized Near-Data Processing with Unrestricted Data Placement for GPUs
Gwangsun Kim, Niladrish Chatterjee, Mike O'Connor, Kevin Hsieh
Understanding Error Propagation in Deep Learning Neural Network (DNN) Accelerators and Applications
Guanpeng Li, Siva Hari, Michael B. Sullivan, Timothy Tsai, Karthik Pattabiraman, Joel Emer, Steve Keckler
Fine-Grained DRAM: Energy-Efficient DRAM for Extreme Bandwidth Systems
Mike O'Connor, Niladrish Chatterjee, Donghyuk Lee, John Wilson, Aditya Agrawal, Steve Keckler, William Dally
Xylem: Enhancing Vertical Thermal Conduction in 3D Processor-Memory Stacks
Aditya Agrawal, Josep Torrellas, Sachin Idgunji
Ambit: In-Memory Accelerator for Bulk Bitwise Operations Using Commodity DRAM Technology
Vivek Seshadri, Donghyuk Lee, Thomas Mullins, Hasan Hassan, Amirali Boroumand, Jeremie Kim, Michael A. Kozuch, Onur Mutlu, Phillip B. Gibbons, Todd C. Mowry
Detecting and Mitigating Data-Dependent DRAM Failures by Exploiting Current Memory Content
Samira Khan, Chris Wilkerson, Zhe Wang, Alaa R. Alameldeen, Donghyuk Lee, Onur Mutlu
RTLCheck: Verifying Memory Consistency in RTL Designs
Yatin A. Manerkar, Daniel Lustig, Margaret Martonosi, Michael Pellauer
IEEE Micro Top Picks in Computer Architecture (Honorable Mention)
Beyond the Socket: NUMA-Aware GPUs
Ugljesa Milic, Oreste Villa, Evgeny Bolotin, Akhil Arunkumar, Eiman Ebrahimi, Aamer Jaleel, Alex Ramirez, David Nellans
Weak Memory Models with Matching Axiomatic and Operational Definitions
Sizhuo Zhang, Muralidaran Vijayaraghavan, Daniel Lustig, Arvind
BATMAN: Maximizing Bandwidth Utilization of Hybrid Memory Systems
Chiachen Chou, Aamer Jaleel, Moinuddin Qureshi
MCM-GPU: Multi-Chip-Module GPUs for Continued Performance Scalability
Akhil Arunkumar , Evgeny Bolotin, Benjamin Cho, Ugljesa Milic , Eiman Ebrahimi, Oreste Villa, Aamer Jaleel, Carole-Jean Wu , David Nellans
SCNN: An Accelerator for Compressed-sparse Convolutional Neural Networks
Angshuman Parashar, Minsoo Rhu, Anurag Mukkara, Antonio Puglielli, Rangharajan Venkatesan, Brucek Khailany, Joel Emer, Steve Keckler, William Dally
Fractal: An Execution Model for Fine-Grain Nested Speculative Parallelism
Suvinay Subramanian, Mark C. Jeffrey, Maleen Abeydeera, Hyun Ryong Lee, Victor A. Ying, Joel Emer, Daniel Sanchez
Understanding Reduced-Voltage Operation in Modern DRAM Devices: Experimental Characterization, Analysis, and Mechanisms
Kevin Chang, Abdullah Giray Yağlıkçı, Saugata Ghose, Aditya Agrawal, Niladrish Chatterjee, Abhijith Kashyap, Donghyuk Lee, Mike O'Connor, Hasan Hassan, Onur Mutlu
Design-Induced Latency Variation in Modern DRAM Chips: Characterization, Analysis, and Latency Reduction Mechanisms
Donghyuk Lee, Samira Khan, Lavanya Subramanian, Saugata Ghose, Rachata Ausavarungnirun, Gennady Pekhimenko, Vivek Seshadri, Onur Mutlu
Understanding Reduced-Voltage Operation in Modern DRAM Chips: Characterization, Analysis, and Mechanisms
Kevin K. Chang, Abdullah Giray Yağlıkçı, Saugata Ghose, Aditya Agrawal, Niladrish Chatterjee, Abhijith Kashyap, Donghyuk Lee, Mike O'Connor, Hasan Hassan, Onur Mutlu
SCNN: An Accelerator for Compressed-sparse Convolutional Neural Networks
Angshuman Parashar, Minsoo Rhu, Anurag Mukkara, Antonio Puglielli, Rangharajan Venkatesan, Brucek Khailany, Joel Emer, Steve Keckler, William Dally
Compressing DMA Engine: Leveraging Activation Sparsity for Training Deep Neural Networks
Minsoo Rhu, Mike O'Connor, Niladrish Chatterjee, Jeff Pool, Stephen W. Keckler
SASSIFI: An Architecture-level Fault Injection Tool for GPU Application Resilience Evaluation
Siva Hari, Timothy Tsai, Mark Stephenson, Steve Keckler, Joel Emer
Automated Synthesis of Comprehensive Memory Model Litmus Test Suites
Daniel Lustig, Andrew Wright, Alexandros Papakonstantinou, Olivier Giroux
TriCheck: Memory Model Verification at the Trisection of Software, Hardware, and ISA
Caroline Trippel, Yatin A. Manerkar, Daniel Lustig, Michael Pellauer, Margaret Martonosi
IEEE Micro Top Picks in Computer Architecture