People

Angshuman Parashar

Dr. Angshuman Parashar joined NVIDIA in 2015 and is a member of the Architecture Research Group. His research focuses on building and evaluating architectures for spatial and data-parallel algorithms. Prior to NVIDIA, he was a member of the VSSAD group at Intel, where he worked with a small team of experts in architecture, languages, workloads and implementation to design and evaluate a new spatial architecture.

Parashar received his Ph.D. in Computer Science and Engineering from the Pennsylvania State University in 2007, and his B.Tech. in Computer Science and Engineering from the Indian Institute of Technology, Delhi in 2002.

List of publications

Research Area(s)
Artificial Intelligence and Machine Learning
Main Field of Interest
Computer Architecture

Publications

2022

Demystifying Map Space Exploration for NPUs
Sheng-Chun Kao, Angshuman Parashar, Po-An Tsai, Tushar Krishna
International Symposium on Workload Characterization (IISWC)
Sparseloop: An Analytical Approach to Sparse Tensor Accelerator Modeling
Yannan Nellie Wu, Po-An Tsai, Angshuman Parashar, Vivienne Sze, Joel Emer
International Symposium on Microarchitecture (MICRO)
Distinguished Artifact award
Ruby: Improving Hardware Efficiency for Tensor Algebra Accelerators Through Imperfect Factorization
Mark Horeni, Pooria Taheri, Po-An Tsai, Angshuman Parashar, Joel Emer, Siddharth Joshi
International Symposium on Performance Analysis of Systems and Software (ISPASS)
A Formalism of DNN Accelerator Flexibility
Sheng-Chun Kao, Hyoukjun Kwon, Michael Pellauer, Angshuman Parashar, Tushar Krishna
SIGMETRICS
DiGamma: Domain-aware Genetic Algorithm for HW-Mapping Co-optimization for DNN Accelerators
Sheng-Chun Kao, Michael Pellauer, Angshuman Parashar, Tushar Krishna
Design, Automation & Test in Europe (DATE)
Marvel: A Data-Centric Approach for Mapping Deep Learning Operators on Spatial Accelerators
Prasanth Chatarasi, Hyoukjun Kwon, Angshuman Parashar, Michael Pellauer, Tushar Krishna, Vivek Sarkar
Transactions on Architecture and Code Optimization (TACO)

2021

Union: A Unified HW-SW Co-Design Ecosystem in MLIR for Evaluating Tensor Operations on Spatial Accelerators
Geonhwa Jeong, Gokcen Kestor, Prasanth Chatarasi, Angshuman Parashar, Po-An Tsai, Sivasankaran Rajamanickam, Roberto Gioiosa, Tushar Krishna
Parallel Architectures and Compilation Techniques (PACT)
Sparseloop: An Analytical, Energy-Focused Design Space Exploration Methodology for Sparse Tensor Accelerators
Yannan Nellie Wu, Po-An Tsai, Angshuman Parashar, Vivienne Sze, Joel Emer
International Symposium on Performance Analysis of Systems and Software (ISPASS)
Mind Mappings: Enabling Efficient Algorithm-Accelerator Mapping Space Search
Kartik Hegde, Po-An Tsai, Sitao Huang, Vikas Chandra, Angshuman Parashar, Christopher W. Fletcher
International Conference on Architectural Support for Programming Languages and…
Hardware Abstractions for Targeting EDDO Architectures with the Polyhedral Model
Angshuman Parashar, Prasanth Chatarasi, Po-An Tsai
International Workshop on Polyhedral Compilation Techniques (IMPACT)
Flexion: A Quantitative Metric for Flexibility in DNN Accelerators
Hyoukjun Kwon, Michael Pellauer, Angshuman Parashar, Tushar Krishna
IEEE Computer Architecture Letters (CAL)

2020

MAESTRO: A Data-Centric Approach to Understand Reuse, Performance, and Hardware Cost of DNN Mappings
Hyoukjun Kwon, Prasanth Chatarasi, Vivek Sarkar, Tushar Krishna, Michael Pellauer, Angshuman Parashar
IEEE Micro (Issue: Top Picks of the 2019 Computer Architecture Conferences)

2019

Understanding Reuse, Performance, and Hardware Cost of DNN Dataflows: A Data-Centric Approach.
Hyoukjun Kwon, Prasanth Chatarasi, Michael Pellauer, Angshuman Parashar, Vivek Sarkar, Tushar Krishna
International Symposium on Microarchitecture (MICRO)
IEEE Micro Top Picks in Computer Architecture
Timeloop: A Systematic Approach to DNN Accelerator Evaluation
Angshuman Parashar, Priyanka Raina, Yakun Sophia Shao, Yu-Hsin Chen, Victor A. Ying, Anurag Mukkara, Rangharajan Venkatesan, Brucek Khailany, Steve Keckler, Joel Emer
International Symposium on Performance Analysis of Systems and Software (ISPASS)

2018

Stitch-X: An Accelerator Architecture for Exploiting Unstructured Sparsity in Deep Neural Networks
Ching-En Lee, Yakun Sophia Shao, Jie-Fang Zhang, Angshuman Parashar, Joel Emer, Steve Keckler, Zhengya Zhang
SysML Conference

2017

SCNN: An Accelerator for Compressed-sparse Convolutional Neural Networks
Angshuman Parashar, Minsoo Rhu, Anurag Mukkara, Antonio Puglielli, Rangharajan Venkatesan, Brucek Khailany, Joel Emer, Steve Keckler, William Dally
International Symposium on Computer Architecture (ISCA)
SCNN: An Accelerator for Compressed-sparse Convolutional Neural Networks
Angshuman Parashar, Minsoo Rhu, Anurag Mukkara, Antonio Puglielli, Rangharajan Venkatesan, Brucek Khailany, Joel Emer, Steve Keckler, William Dally
arXiv

2015

Efficient Control and Communication Paradigms for Coarse-Grained Spatial Architectures
Michael Pellauer, Angshuman Parashar, Michael Adler, Bushra Ahsan, Randy Almon, Neal Crago, Kermin Fleming, Mohit Gambhir, Aamer Jaleel, Tushar Krishna, Daniel Lustig, Stephen Maresh, Vladimir Pavlov, Rachid Rayess, Antonia Zhai, Joel Emer
ACM Transactions on Computing Systems (TOCS)