People

Steve Keckler

Steve Keckler joined NVIDIA in 2009 and leads the Architecture Research Group. He is also an Adjunct Professor of Computer Science at the University of Texas at Austin, where he served on the faculty from 1998-2012. His research interests include parallel computer architectures, high-performance computing, energy-efficient architectures, and embedded computing.  Dr. Keckler was previously at the Massachusetts Institute of Technology from 1990 to 1998, where he led the development of the M-Machine experimental parallel computer system. He is a Fellow of the ACM, a Fellow of the IEEE, an Alfred P. Sloan Research Fellow, and a recipient of the NSF CAREER award, the ACM Grace Murray Hopper award, the President's Associates Teaching Excellence Award at UT-Austin, and the Edith and Peter O’Donnell award for Engineering. He earned a B.S. in Electrical Engineering from Stanford University and an M.S. and a Ph.D. in Computer Science from the Massachusetts Institute of Technology. Full list of publications

Research Area(s)
Computer Architecture
Computer Vision
High Performance Computing
Artificial Intelligence and Machine Learning
Resilience and Safety
Main Field of Interest
Computer Architecture
Google Scholar
https://scholar.google.com/citations?user=PpjjRvoAAAAJ&hl=en

Publications

2023

cuCatch: A Debugging Tool for Efficiently Catching Memory Safety Violations in CUDA Applications
Mohamed Tarek Ibn Ziad, Sana Damani, Aamer Jaleel, Stephen W. Keckler, Mark Stephenson
ACM SIGPLAN Conference on Programming Language Design and Implementation (PLDI)

2022

Augmenting Legacy Networks for Flexible Inference.
Jason Clemons, Iuri Frosio, Maying Shen, Jose M. Alvarez, Steve Keckler
Workshop on Computational Aspects of Deep Learning (CADL)
Zhuyi: Perception Processing Rate Estimation for Safety in Autonomous Vehicles
Yu-Shun Hsiao, Siva Hari, Michał Filipiuk, Timothy Tsai, Michael B. Sullivan, Vijay Janapa Reddi, Vasu Singh, Steve Keckler
Design Automation Conference (DAC)
Exploiting Temporal Data Diversity for Detecting Safety-critical Faults in AV Compute Systems
Saurabh Jha, Shengkun Cui, Timothy Tsai, Siva Hari, Michael B. Sullivan, Zbigniew T. Kalbarczyk, Steve Keckler, Ravishankar K. Iyer
International Conference on Dependable Systems and Networks (DSN)
Zhuyi: Perception Processing Rate Estimation for Safety in Autonomous Vehicles
Yu-Shun Hsiao, Siva Hari, Michał Filipiuk, Timothy Tsai, Michael B. Sullivan, Vijay Janapa Reddi, Vasu Singh, Steve Keckler
arXiv
Saving PAM4 Bus Energy with SMOREs: Sparse Multi-level Opportunistic Restricted Encodings
Mike O'Connor, Donghyuk Lee, Niladrish Chatterjee, Michael B. Sullivan, Steve Keckler
International Symposium on High-Performance Computer Architecture (HPCA)
Characterizing and Mitigating Soft Errors in GPU DRAM
Michael B. Sullivan, Nirmal R. Saxena, Mike O'Connor, Donghyuk Lee, Paul Racunas, Saurabh Hukerikar, Timothy Tsai, Siva Kumar Sastry Hari, Stephen W. Keckler
IEEE Micro (Issue: Top Picks of the 2021 Computer Architecture Conferences)
GPU Subwarp Interleaving
Sana Damani, Mark Stephenson, Ram Rangan, Daniel Johnson, Rishkul Kulkarni, Steve Keckler
International Symposium on High-Performance Computer Architecture (HPCA)
Accelerators
Steve Keckler, Dejan Milojicic
IEEE Computer

2021

GPU Domain Specialization via Composable On-Package Architecture
Yaosheng Fu, Evgeny Bolotin, Niladrish Chatterjee, David Nellans, Steve Keckler
ACM Transactions on Architecture and Code Optimization (TACO)
Evolution of the Graphics Processing Unit (GPU)
William Dally, Steve Keckler, David B. Kirk
IEEE Micro Special Issue of the 50th Anniversary of the Microprocessor
Optimizing Selective Protection for CNN Resilience
Abdulrahman Mahmoud, Siva Hari, Christopher W. Fletcher, Sarita V. Adve, Charbel Sakr, Naresh Shanbhag, Pavlo Molchanov, Michael B. Sullivan, Timothy Tsai, Steve Keckler
International Symposium on Software Reliability Engineering (ISSRE)
Suraksha: A Framework to Analyze the Safety Implications of Perception Design Choices in AVs
Hengyu Zhao, Siva Hari, Timothy Tsai, Michael B. Sullivan, Steve Keckler, Jishen Zhao
International Symposium on Software Reliability Engineering (ISSRE)
Characterizing and Mitigating Soft Errors in GPU DRAM
Michael B. Sullivan, Nirmal Saxena, Mike O'Connor, Donghyuk Lee, Paul Racunas, Saurabh Hukerikar, Timothy Tsai, Siva Hari, Steve Keckler
International Symposium on Microarchitecture (MICRO)
IEEE Micro Top Picks in Computer Architecture
Generating and Characterizing Scenarios for Safety Testing of Autonomous Vehicles
Zahra Ghodsi, Siva Hari, Iuri Frosio, Timothy Tsai, Alejandro Troccoli, Steve Keckler, Siddharth Garg, Anima Anandkumar
IEEE Intelligent Vehicles Symposium (IV)
Cooperative Profile Guided Optimization
Mark Stephenson, Ram Rangan, Steve Keckler
Computer Graphics Forum (Proceedings of High Performance Graphics)
NVBitFI: Dynamic Fault Injection for GPUs
Timothy Tsai, Siva Hari, Michael B. Sullivan, Oreste Villa, Steve Keckler
International Conference on Dependable Systems and Networks (DSN)
Suraksha: A Quantitative AV Safety Evaluation Framework to Analyze Safety Implications of Perception Design Choices
Hengyu Zhao, Siva Hari, Timothy Tsai, Michael B. Sullivan, Steve Keckler, Jishen Zhao
Workshop on Safety and Security of Intelligent Vehicles (SSIV)
Simba: scaling deep-learning inference with chiplet-based architecture
Yakun Sophia Shao, Jason Clemons, Rangharajan Venkatesan, Brian Zimmer, Matt Fojtik, Ted Jiang, Ben Keller, Alicia Klinefelter, Nathaniel Pinckney, Priyanka Raina, Stephen Tell, Yanqing Zhang, William Dally, Joel Emer, Tom Gray, Brucek Khailany, Steve Keckler
Communications of the ACM
ACM Research Highlight
GPU Domain Specialization via Composable On-Package Architecture
Yaosheng Fu, Evgeny Bolotin, Niladrish Chatterjee, David Nellans, Steve Keckler
arXiv
Generating and Characterizing Scenarios for Safety Testing of Autonomous Vehicles
Zahra Ghodsi, Siva Hari, Iuri Frosio, Timothy Tsai, Alejandro Troccoli, Steve Keckler, Siddharth Garg, Anima Anandkumar
arXiv
Making Convolutions Resilient via Algorithm-Based Error Detection Techniques
Siva Hari, Michael B. Sullivan, Timothy Tsai, Steve Keckler
IEEE Transactions on Dependable and Secure Computing (TDSC)
SNAP: An Efficient Sparse Neural Acceleration Processor for Unstructured Sparse Deep Neural Network Inference
Jie-Fang Zhang, Ching-En Lee, Chester Liu, Yakun Sophia Shao, Steve Keckler, Zhengya Zhang
IEEE Journal of Solid-State Circuits (JSSC)

2020

Generating and Characterizing Scenarios for Safety Testing of Autonomous Vehicles
Zahra Ghodsi, Siva Hari, Iuri Frosio, Timothy Tsai, Alejandro Troccoli, Steve Keckler, Siddharth Garg, Anima Anandkumar
IEEE International Workshop on Automotive Reliability & Test (ART)
Generating and Characterizing Scenarios for Safety Testing of Autonomous Vehicles
Zahra Ghodsi, Siva Hari, Iuri Frosio, Timothy Tsai, Alejandro Troccoli, Steve Keckler, Siddharth Garg, Anima Anandkumar
IEEE Automotive Reliability and Test Workshop
HarDNN: Fine-Grained Vulnerability Evaluation and Protection for Convolutional Neural Networks
Abdulrahman Mahmoud, Siva Hari, Christopher W. Fletcher, Sarita V. Adve, Charbel Sakr, Naresh Shanbhag, Pavlo Molchanov, Michael B. Sullivan, Timothy Tsai, Steve Keckler
SRC TECHCON
Making Convolutions Resilient via Algorithm-Based Error Detection Techniques
Siva Hari, Michael B. Sullivan, Timothy Tsai, Steve Keckler
arXiv
Buddy Compression: Enabling Larger Memory for Deep Learning and HPC Workloads on GPUs
Esha Chouske, Michael B. Sullivan, Mike O'Connor, Mattan Erez, Jeff Pool, David Nellans, Steve Keckler
International Symposium on Computer Architecture (ISCA)
Estimating Silent Data Corruption Rates Using a Two-Level Model
Siva Hari, Paolo Rech, Timothy Tsai, Mark Stephenson, Arslan Zulfiqar, Michael B. Sullivan, Philip Shirvani, Paul Racunas, Joel Emer, Steve Keckler
arXiv
Feature Map Vulnerability Evaluation in CNNs
Abdulrahman Mahmoud, Siva Hari, Christopher W. Fletcher, Sarita V. Adve, Charbel Sakr, Naresh Shanbhag, Pavlo Molchanov, Michael B. Sullivan, Timothy Tsai, Steve Keckler
Workshop on Secure and Resilient Autonomy
HarDNN: Feature Map Vulnerability Evaluation in CNNs
Abdulrahman Mahmoud, Siva Hari, Christopher W. Fletcher, Sarita V. Adve, Charbel Sakr, Naresh Shanbhag, Pavlo Molchanov, Michael B. Sullivan, Timothy Tsai, Steve Keckler
arXiv
Speculative Reconvergence for Improved SIMT Efficiency
Sana Damani, Daniel Johnson, Mark Stephenson, Eddie Yan, Olivier Giroux, Michael McKeown, Steve Keckler
International Symposium on Code Generation and Optimization
A 0.32–128 TOPS, Scalable Multi-Chip-Module-Based Deep Neural Network Inference Accelerator With Ground-Referenced Signaling in 16 nm
Brian Zimmer, Rangharajan Venkatesan, Yakun Sophia Shao, Jason Clemons, Matt Fojtik, Ted Jiang, Ben Keller, Alicia Klinefelter, Nathaniel Pinckney, Priyanka Raina, Stephen Tell, Yanqing Zhang, William Dally, Joel Emer, Tom Gray, Steve Keckler, Brucek Khailany
IEEE Journal of Solid-State Circuits (JSSC)
JSSC 2020 Best Paper award

2019

MAGNet: A Modular Accelerator Generator for Neural Networks
Rangharajan Venkatesan, Sophia Shao, Miaorong Wang, Jason Clemons, Steve Dai, Matt Fojtik, Ben Keller, Alicia Klinefelter, Nathaniel Pinckney, Priyanka Raina, Yanqing Zhang, Brian Zimmer, William Dally, Joel Emer, Steve Keckler, Brucek Khailany
International Conference On Computer Aided Design (ICCAD)
NVBit: A Dynamic Binary Instrumentation Framework for NVIDIA GPUs
Oreste Villa, Mark Stephenson, David Nellans, Steve Keckler
International Symposium on Microarchitecture (MICRO)
Simba: Scaling Deep-Learning Inference with Multi-Chip-Module-Based Architecture
Sophia Shao, Jason Clemons, Rangharajan Venkatesan, Brian Zimmer, Matt Fojtik, Ted Jiang, Ben Keller, Alicia Klinefelter, Nathaniel Pinckney, Priyanka Raina, Stephen Tell, Yanqing Zhang, William Dally, Joel Emer, Tom Gray, Brucek Khailany, Steve Keckler
International Symposium on Microarchitecture (MICRO)
Best Paper award, IEEE Micro Top Picks in Computer Architecture (Honorable Mention)
A 0.11 pJ/Op, 0.32-128 TOPS, Scalable Multi-Chip-Module-based Deep Neural Network Accelerator Designed with a High-Productivity VLSI Methodology
Rangharajan Venkatesan, Sophia Shao, Brian Zimmer, Jason Clemons, Matt Fojtik, Ted Jiang, Ben Keller, Alicia Klinefelter, Nathaniel Pinckney, Priyanka Raina, Stephen Tell, Yanqing Zhang, William Dally, Joel Emer, Tom Gray, Steve Keckler, Brucek Khailany
Hot Chips: A Symposium on High Performance Chips
ML-based Fault Injection for Autonomous Vehicles: A Case for Bayesian Fault Injection
Saurabh Jha, Subho S. Banerjee, Timothy Tsai, Siva Hari, Michael B. Sullivan, Zbigniew T. Kalbarczyk, Steve Keckler, Ravishankar K. Iyer
arXiv
Kayotee: A Fault Injection-based System to Assess the Safety and Reliability of Autonomous Vehicles to Faults and Errors
Saurabh Jha, Timothy Tsai, Siva Hari, Michael B. Sullivan, Zbigniew Kalbarczyk, Steve Keckler, Ravishankar K. Iyer
arXiv
GPU Snapshot: Checkpoint Offloading for GPU-Dense Systems
Kyushick Lee, Michael B. Sullivan, Siva Hari, Timothy Tsai, Steve Keckler, Mattan Erez
International Conference on Supercomputing
ML-based Fault Injection for Autonomous Vehicles: A Case for Bayesian Fault Injection
Saurabh Jha, Subho Banerjee, Timothy Tsai, Siva Hari, Michael B. Sullivan, Zbigniew T. Kalbarczyk, Steve Keckler, Ravishankar K. Iyer
International Conference on Dependable Systems and Networks (DSN)
On the Trend of Resilience for GPU-Dense Systems
Kyushick Lee, Michael B. Sullivan, Siva Hari, Timothy Tsai, Steve Keckler, Mattan Erez
International Conference on Dependable Systems and Networks, Supplemental (DSN-…
Best of SELSE (Workshop on Silicon Errors in Logic - System Effects)
A 0.11 pJ/Op, 0.32-128 TOPS, Scalable Multi-Chip-Module-based Deep Neural Network Accelerator with Ground-Reference Signaling in 16nm
Brian Zimmer, Rangharajan Venkatesan, Sophia Shao, Jason Clemons, Matt Fojtik, Ted Jiang, Ben Keller, Alicia Klinefelter, Nathaniel Pinckney, Priyanka Raina, Stephen Tell, Yanqing Zhang, William Dally, Joel Emer, Tom Gray, Steve Keckler, Brucek Khailany
Symposium on VLSI Circuits
SNAP: A 1.67 – 21.55 TOPS/W Sparse Neural Acceleration Processor for Unstructured Sparse Deep Neural Network Inference in 16nm CMOS
Jie-Fang Zhang, Ching-En Lee, Chester Liu, Yakun Sophia Shao, Steve Keckler, Zhengya Zhang
Symposia on VLSI Technology and Circuits (VLSI)
Buffets: An Efficient and Composable Storage Idiom for Explicit Decoupled Data Orchestration
Michael Pellauer, Yakun Sophia Shao, Jason Clemons, Neal Crago, Kartik Hegde, Rangharajan Venkatesan, Steve Keckler, Christopher W. Fletcher, Joel Emer
International Conference on Architectural Support for Programming Languages and…
IEEE Micro Top Picks in Computer Architecture (Honorable Mention)
On the Trend of Resilience for GPU-Dense Systems
Kyushick Lee, Michael B. Sullivan, Siva Hari, Timothy Tsai, Steve Keckler, Mattan Erez
IEEE Workshop on Silicon Errors in Logic – System Effects (SELSE)
Award paper
Timeloop: A Systematic Approach to DNN Accelerator Evaluation
Angshuman Parashar, Priyanka Raina, Yakun Sophia Shao, Yu-Hsin Chen, Victor A. Ying, Anurag Mukkara, Rangharajan Venkatesan, Brucek Khailany, Steve Keckler, Joel Emer
International Symposium on Performance Analysis of Systems and Software (ISPASS)

2018

Optimizing Software-Directed Instruction Replication for GPU Error Detection
Abdulrahman Mahmoud, Siva Hari, Michael B. Sullivan, Timothy Tsai, Steve Keckler
International Conference for High-Performance Computing, Networking, Storage a…
Kayotee: A Fault Injection-based System to Assess the Safety and Reliability of Autonomous Vehicles to Faults and Errors
Saurabh Jha, Timothy Tsai, Siva Hari, Michael B. Sullivan, Zbigniew Kalbarczyk, Steve Keckler, Ravishankar K. Iyer
Third IEEE International Workshop on Automotive Reliability & Test
SwapCodes: Error Codes for Hardware-Software Cooperative GPU Pipeline Error Detection
Michael B. Sullivan, Siva Hari, Brian Zimmer, Timothy Tsai, Stephen W. Keckler
The International Symposium on Microarchitecture (MICRO)
Exposing Memory Access Patterns to Improve Instruction and Memory Efficiency in GPUs
Neal Crago, Mark Stephenson, Steve Keckler
ACM Transactions on Architecture and Code Optimization (TACO)
Software-Directed Techniques for Improved GPU Register File Utilization
Dani Voitsechov, Arslan Zulfiqar, Mark Stephenson, Mark Gebhart, Steve Keckler
ACM Transactions on Architecture and Code Optimization (TACO)
Structurally Sparsified Backward Propagation for Faster Long Short-Term Memory Training
Maohua Zhu, Jason Clemons, Jeff Pool, Minsoo Rhu, Steve Keckler, Yuan Xie
arXiv
Compressing DMA Engine: Leveraging Activation Sparsity for Training Deep Neural Networks
Minsoo Rhu, Mike O'Connor, Niladrish Chatterjee, Jeff Pool, Youngeun Kwon, Steve Keckler
International Symposium on High Performance Computer Architecture (HPCA)
Stitch-X: An Accelerator Architecture for Exploiting Unstructured Sparsity in Deep Neural Networks
Ching-En Lee, Yakun Sophia Shao, Jie-Fang Zhang, Angshuman Parashar, Joel Emer, Steve Keckler, Zhengya Zhang
SysML Conference

2017

Understanding Error Propagation in Deep Learning Neural Network (DNN) Accelerators and Applications
Guanpeng Li, Siva Hari, Michael B. Sullivan, Timothy Tsai, Karthik Pattabiraman, Joel Emer, Steve Keckler
The International Conference for High Performance Computing, Networking, Storag…
Fine-Grained DRAM: Energy-Efficient DRAM for Extreme Bandwidth Systems
Mike O'Connor, Niladrish Chatterjee, Donghyuk Lee, John Wilson, Aditya Agrawal, Steve Keckler, William Dally
International Symposium on Microarchitecture (MICRO)
SCNN: An Accelerator for Compressed-sparse Convolutional Neural Networks
Angshuman Parashar, Minsoo Rhu, Anurag Mukkara, Antonio Puglielli, Rangharajan Venkatesan, Brucek Khailany, Joel Emer, Steve Keckler, William Dally
International Symposium on Computer Architecture (ISCA)
SCNN: An Accelerator for Compressed-sparse Convolutional Neural Networks
Angshuman Parashar, Minsoo Rhu, Anurag Mukkara, Antonio Puglielli, Rangharajan Venkatesan, Brucek Khailany, Joel Emer, Steve Keckler, William Dally
arXiv
Compressing DMA Engine: Leveraging Activation Sparsity for Training Deep Neural Networks
Minsoo Rhu, Mike O'Connor, Niladrish Chatterjee, Jeff Pool, Stephen W. Keckler
arXiv
SASSIFI: An Architecture-level Fault Injection Tool for GPU Application Resilience Evaluation
Siva Hari, Timothy Tsai, Mark Stephenson, Steve Keckler, Joel Emer
International Symposium on Performance Analysis of Systems and Software (ISPASS)
Architecting an Energy-Efficient DRAM System for GPUs
Niladrish Chatterjee, Mike O'Connor, Donghyuk Lee, Daniel Johnson, Minsoo Rhu, Steve Keckler, William Dally
International Symposium on High Performance Computer Architecture (HPCA)

2016

A Patch Memory System For Image Processing and Computer Vision.
Jason Clemons, Chih-Chi Cheng, Iuri Frosio, Daniel Johnson, Steve Keckler
International Symposium on Microarchitecture (MICRO)
vDNN: Virtualized Deep Neural Networks for Scalable, Memory-Efficient Neural Network Design.
Minsoo Rhu, Natalia Gimelshein, Jason Clemons, Arslan Zulfiqar, Steve Keckler
International Symposium on Microarchitecture (MICRO)
CLARA: Circular Linked-List Auto- and Self-Refresh Architecture
Aditya Agrawal, Mike O'Connor, Evgeny Bolotin, Niladrish Chatterjee, Joel Emer, Steve Keckler
International Symposium on Memory Systems (MEMSYS'16)
Transparent Offloading and Mapping (TOM): Enabling Programmer-Transparent Near-Data Processing in GPU Systems
Kevin Hsieh, Eiman Ebrahimi, Gwangsun Kim, Niladrish Chatterjee, Mike O'Connor, Nandita Vijaykumar, Onur Mutlu, Steve Keckler
International Symposium on Computer Architecture (ISCA)
A Real-time Energy-Efficient Superpixel Hardware Accelerator for Mobile Computer Vision Applications
Injoon Hong, Jason Clemons, Rangharajan Venkatesan, Iuri Frosio, Brucek Khailany, Steve Keckler
Design Automation Conference (DAC)
Selective GPU Caches to Eliminate CPU-GPU HW Cache Coherence
Neha Agarwal, David Nellans, Eiman Ebrahimi, Thomas F. Wenisch, John Danskin, Steve Keckler
International Symposium on High Performance Computer Architecture (HPCA)
Towards High Performance Paged Memory for GPUs
Tianhao Zheng, David Nellans, Arslan Zulfiqar, Mark Stephenson, Steve Keckler
International Symposium on High Performance Computer Architecture (HPCA)
A Case for Toggle-Aware Compression for GPU Systems
Gennady Pekhimenko, Evgeny Bolotin, Nandita Vijaykumar, Onur Mutlu, Todd C. Mowry, Steve Keckler
International Symposium on High Performance Computer Architecture (HPCA)
An Analytical Model for Hardened Latch Selection and Exploration
Michael B. Sullivan, Brian Zimmer, Siva Hari, Timothy Tsai, Steve Keckler
Workshop on Silicon Errors in Logic--System Effects (SELSE)
vDNN: Virtualized Deep Neural Networks for Scalable, Memory-Efficient Neural Network Design
Minsoo Rhu, Natalia Gimelshein, Jason Clemons, Arslan Zulfiqar, Steve Keckler
arXiv

2015

Anatomy of GPU Memory System for Multi-Application Execution
Adwait Jog, Onur Kayiran, Tuba Kesten, Ashutosh Pattnaik, Evgeny Bolotin, Niladrish Chatterjee, Steve Keckler, Mahmut T. Kandemir, Chita R. Das
International Symposium on Memory Systems (MEMSYS)
GPU Computing Pipeline Inefficiencies and Optimization Opportunities in Heterogeneous CPU-GPU Processors
Joel Hestness, Steve Keckler, David A. Wood
International Symposium on Workload Characterization (IISWC)
Designing Efficient Heterogeneous Memory Architectures
Evgeny Bolotin, David Nellans, Oreste Villa, Mike O'Connor, Alex Ramirez, Steve Keckler, Mike O'Connor
IEEE Micro
A Variable Warp Size Architecture
Timothy Rogers, Daniel Johnson, Mike O'Connor, Steve Keckler
International Symposium on Computer Architecture (ISCA)
Flexible Software Profiling of GPU Architectures
Mark Stephenson, Siva Hari, Yunsup Lee, Eiman Ebrahimi, Daniel Johnson, David Nellans, Mike O'Connor, Steve Keckler
International Symposium on Computer Architecture (ISCA)
Toggle-aware Compression for GPUs
Gennady Pekhimenko, Evgeny Bolotin, Mike O'Connor, Onur Mutlu, Todd C. Mowry, Steve Keckler
IEEE Computer Architecture Letters ( Volume: 14, Issue: 2, July-Dec. 1 2015 )
SASSIFI: Evaluating Resilience of GPU Applications
Siva Hari, Timothy Tsai, Mark Stephenson, Steve Keckler, Joel Emer
Workshop on Silicon Errors in Logic - System Effects (SELSE-11)
Page Placement Strategies for GPUs within Heterogeneous Memory Systems
Neha Agarwal, David Nellans, Mark Stephenson, Mike O'Connor, Steve Keckler
International Conference on Architectural Support for Programming Languages and…
Priority-Based Cache Allocation in Throughput Processors
Dong Li, Minsoo Rhu, Daniel Johnson, Mike O'Connor, Mattan Erez, Donald Fussell, Steve Keckler
International Symposium on High Performance Computer Architecture (HPCA)
Unlocking Bandwidth for GPUs in CC-NUMA systems
Neha Agarwal, David Nellans, Mike O'Connor, Steve Keckler, Thomas Wenisch
International Symposium on High Performance Computer Architecture (HPCA)

2014

Arbitrary Modulus Indexing
Jeffrey R. Diamond, Donald S. Fussell, Steve Keckler
International Symposium on Microarchitecture (MICRO)
Exploring the Design Space of SPMD Divergence Management on Data-Parallel Architectures
Yunsup Lee, Vinod Grover, Ronny Krashinsky, Mark Stephenson, Steve Keckler, Krste Asanovic
International Symposium on Microarchitecture (MICRO)
Scaling the Power Wall: A Path to Exascale
Oreste Villa, Daniel Johnson, Mike O'Connor, Evgeny Bolotin, David Nellans, Justin Luitjens, Nikolai Sakharnykh, Peng Wang, Paulius Micikevicius, Anthony Scudiero, Steve Keckler, William Dally
SC '14
A Comparative Analysis of Microarchitecture Effects on CPU and GPU Memory System Behavior
Joel Hestness, Steve Keckler, David A. Wood
International Symposium on Workload Characterization (IISWC)
Measuring the Radiation Reliability of SRAM Structures in GPUs Designed for HPC
Paolo Rech, Luigi Carro, Nicholas Wang, Timothy Tsai, Siva Hari, Steve Keckler
Workshop on Silicon Errors in Logic - System Effects (SELSE-10)
Application-aware Memory System for Fair and Efficient Execution of Concurrent GPGPU Applications
Adwait Jog, Evgeny Bolotin, Zvika Guz, Mike Parker, Steve Keckler, Mahmut T. Kandemir, Chita R. Das
Workshop on General Purpose Processing Using GPUs (GPGPU-7)

2013

21st Century Digital Design Tools
William Dally, Chris Malachosky, Steve Keckler
Design Automation Conference (DAC)
Convergence and Scalarization for Data-Parallel Architectures
Yunsup Lee, Ronny Krashinsky, Vinod Grover, Steve Keckler, Krste Asanovic
International Symposium on Code Generation and Optimization (CGO)

2012

Unifying Primary Cache, Scratch, and Register File Memories in a Throughput Processor
Mark Gebhart, Steve Keckler, Brucek Khailany, Ronny Krashinsky, William Dally
International Symposium on Microarchitecture (MICRO)
A Hierarchical Thread Scheduler and Register File for Energy-Efficient Throughput Processors
Mark Gebhart, Daniel R. Johnson, David Tarjan, Steve Keckler, William Dally, Erik Lindholm, Kevin Skadron
ACM Transactions on Computer Systems (TOCS)

2011

A Compile-Time Managed Multi-Level Register File Hierarchy
Mark Gebhart, Steve Keckler, William Dally
International Symposium on Microarchitecture (MICRO)
GPUs and the Future of Parallel Computing
Steve Keckler, William Dally, Brucek Khailany, Michael Garland, David Glasco
IEEE Micro
Energy-efficient Mechanisms for Managing Thread Context in Throughput Processors
Mark Gebhart, Daniel R. Johnson, David Tarjan, Steve Keckler, William Dally, Erik Lindholm, Kevin Skadron
International Symposium on Computer Architecture (ISCA)