Publications | Research

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Circuits and VLSI Design

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2024

DRC-Coder: Automated DRC Checker Code Generation Using LLM Autonomous Agent

Chen-Chia Chang, Chia-Tung (Mark) Ho, Yaguang Li, Yiran Chen, Mark Haoxing Ren

VerilogCoder: Autonomous Verilog Coding Agents with Graph-based Planning and Abstract Syntax Tree (AST)-based Waveform Tracing Tool

Chia-Tung (Mark) Ho, Mark Haoxing Ren, Brucek Khailany

Large Language Model (LLM) for Standard Cell Layout Design Optimization

Chia-Tung (Mark) Ho, Mark Haoxing Ren

Best Paper Award

GL0AM: GPU Accelerated Gate Level Logic Simulator

Yanqing Zhang, Mark Haoxing Ren, Brucek Khailany

Learning to Compare Hardware Designs for High-Level Synthesis

Yunsheng Bai, Atefeh Sohrabizadeh, Zijian Ding, Rongjian Liang, Weikai Li, Ding Wang, Mark Haoxing Ren, Yizhou Sun, Jason Cong

A 0.190-pJ/bit 25.2-Gb/s/wire Inverter-Based AC-Coupled Transceiver for Short-Reach Die-to-Die Interfaces in 5-nm CMOS

Yoshinori Nishi, John W. Poulton, Xi Chen, Sanquan Song, Brian Zimmer, Walker Turner, Stephen Tell, Nikola Nedovic, John Wilson, William Dally, Tom Gray

BoolGebra: Attributed Graph-learning for Boolean Algebraic Manipulation

Yingjie Li, Anthony Agnesina, Yanqing Zhang, Mark Haoxing Ren, Cunxi Yu

Novel Transformer Model Based Clustering Method for Standard Cell Design Automation

Chia-Tung (Mark) Ho, Ajay Chandna, David Guan, Alvin Ho, Minsoo Kim, Yaguang Li, Mark Haoxing Ren

ISPD

Best Paper Award

MedPart: A Multi-Level Evolutionary Differentiable Hypergraph Partitioner

Rongjian Liang, Anthony Agnesina, Mark Haoxing Ren

GPU/ML-Enhanced Large Scale Global Routing Contest

Rongjian Liang, Anthony Agnesina, Wen-Hao Liu, Mark Haoxing Ren

2007

A 14-mW 6.25-Gb/s Transceiver in 90-nm CMOS

John Poulton, Robert Palmer, Andy Fuller, Trey Greer, John Eyles, William Dally, Mark Horowitz