People

Walker Turner

Walker Turner is a Senior Research Scientist in the Circuits Research Group at NVIDIA, Durham, North Carolina. He received the B.S., M.S., and Ph.D. degrees in Electrical Engineering from the University of Florida in 2009, 2012, and 2015, respectively. His research interests include low-power integrated circuit design for mixed-signal and high-speed signaling applications for on- and off-chip communication. Walker is also a Teaching, Assistant Professor at North Carolina State University where he instructs an undergraduate microelectronics engineering course.

 

Main Field of Interest
Circuits and VLSI Design

Publications

2023

Reinforcement Learning Guided Detailed Routing for Custom Circuits
Hao Chen, Kai-Chieh Hsu, Walker Turner, Po-Hsuan Wei, Keren Zhu, David Z. Pan, Haoxing (Mark) Ren
International Symposium on Physical Design 2023

2022

TAG: Learning Circuit Spatial Embedding from Layouts
Keren Zhu, Hao Chen, Walker Turner, George F. Kokai, Po-Hsuan Wei, David Z. Pan, Mark Ren
2022 International Conference on Computer-Aided Design
A 0.297-pJ/bit 50.4-Gb/s/wire Inverter-Based Short-Reach Simultaneous Bidirectional Transceiver for Die-to-Die Interface in 5nm CMOS
Yoshinori Nishi, John W. Poulton, Xi Chen, Sanquan Song, Brian Zimmer, Walker Turner, Stephen Tell, Nikola Nedovic, John Wilson, William Dally, Tom Gray
2022 IEEE SYMPOSIUM ON VLSI TECHNOLOGY & CIRCUITS
AutoCRAFT: Layout Automation for Custom Circuits in Advanced FinFET Technologies
Hao Chen, Walker Turner, Sanquan Song, Keren Zhu, George Kokai, Brian Zimmer, Tom Gray, Brucek Khailany, Mark Ren
International Symposium on Physical Design 2022
Routability-Aware Placement for Advanced FinFET Analog Circuits with Satisfiability Modulo Theories
Hao Chen, Walker Turner, David Z. Pan, Mark Ren
Design, Automation & Test in Europe 2022

2021

Parasitic-Aware Analog Circuit Sizing with Graph Neural Networks and Bayesian Optimization
Mingjie Liu, Walker Turner, George Kokai, David Z. Pan, Brucek Khailany, Mark Ren
2021 Design, Automation & Test in Europe Conference & Exhibition (DATE)

2020

ParaGraph: Layout Parasitics and Device Parameter Prediction using Graph Neural Networks
Mark Ren, George Kokai, Walker Turner, Ting-Sheng Ku
Design Automation Conference (DAC) 2020
Reference-Noise Compensation Scheme for Single- Ended Package-to-Package Links
Xi Chen, Nikola Nedovic, Stephen Tell, Sudhir Kudva, Brian Zimmer, Trey Greer, John Poulton, Sanquan Song, Walker Turner, John Wilson, Tom Gray
2020 International Solid-State Circuits Conference

2019

A 1.17-pJ/b, 25-Gb/s/pin Ground-Referenced Single-Ended Serial Link for Off- and On-Package Communication Using a Process- and Temperature-Adaptive Voltage Regulator
John Poulton, John Wilson, Walker Turner, Brian Zimmer, Xi Chen, Sudhir Kudva, Sanquan Song, Stephen Tell, Nikola Nedovic, Wenxu Zhao, Sunil Sudhakaran, Tom Gray, William Dally
IEEE JOURNAL OF SOLID-STATE CIRCUITS

2018

Ground-Referenced Signaling for Intra-Chip and Short-Reach Chip-to-Chip Interconnects
Walker Turner, John Poulton, John Wilson, Xi Chen, Stephen Tell, Matt Fojtik, Trey Greer, Brian Zimmer, Sanquan Song, Nikola Nedovic, Sudhir Kudva, Sunil Sudhakaran, Rizwan Bashirullah, Wenxu Zhao, William Dally, Tom Gray
Custom Integrated Circuits Conference
A 1.17pJ/b 25Gb/s/pin Ground-Referenced Single Ended Serial Link for Off- and On-Package Communication in 16nm CMOS Using a Process- and Temperature-Adaptive Voltage Regulator
John Wilson, Walker Turner, John Poulton, Brian Zimmer, Xi Chen, Sanquan Song, Stephen Tell, Nikola Nedovic, Wenxu Zhao, Sunil Sudhakaran, Tom Gray, William Dally
ISSCC