People

Yanqing Zhang

Yanqing joined NVIDIA Research in January of 2014. Prior to joining nVidia, he was a research assistant at the Robust Low Power VLSI research group at the University of Virginia (UVA),  where he received his PhD degree in 2013. While at UVA, his research focuses were on low power SoCs, sub-threshold digital circuit design, variation aware timing closure, and variation aware circuit design. Since joining NVIDIA, his research directions include machine learning for EDA applications, digital VLSI methodology, variation resilient digital design, and latch-based timing.

Research Area(s)
Circuits and VLSI Design
Main Field of Interest
Circuits and VLSI Design
Google Scholar
https://scholar.google.com/citations?view_op=list_works&hl=en&user=CLbekz4AAAAJ…

Publications

2022

XT-PRAGGMA: Crosstalk Pessimism Reduction Accessible by GPU Gate-level Simulations and Machine Learning
Vidya Chhabria, Ben Keller, Yanqing Zhang, Sandeep Vollala, Sreedhar Patty, Mark Ren, Brucek Khailany
MLCAD '22: Proceedings of the 2022 ACM/IEEE Workshop on Machine Learning for CAD
From RTL to CUDA: A GPU Acceleration Flow for RTL Simulation with Batch Stimulus
Dian-Lun Lin, Mark Ren, Yanqing Zhang, Brucek Khailany, Tsung-Wei Huang
51st International Conference on Parallel Processing (ICPP '22)
GATSPI: GPU Accelerated Gate-Level Simulation for Power Improvement
Yanqing Zhang, Mark Ren, Akshay Sridharan, Brucek Khailany
2022 Design Automation Conference
Machine Learning and Algorithms: Let Us Team Up for EDA
Mark Ren, Brucek Khailany, Matt Fojtik, Yanqing Zhang
IEEE Design & Test

2021

Simba: scaling deep-learning inference with chiplet-based architecture
Yakun Sophia Shao, Jason Clemons, Rangharajan Venkatesan, Brian Zimmer, Matt Fojtik, Ted Jiang, Ben Keller, Alicia Klinefelter, Nathaniel Pinckney, Priyanka Raina, Stephen Tell, Yanqing Zhang, William Dally, Joel Emer, Tom Gray, Brucek Khailany, Steve Keckler
Communications of the ACM
MAVIREC: ML-Aided Vectored IR-Drop Estimation and Classification
Vidya A. Chhabria, Yanqing Zhang, Mark Ren, Ben Keller, Brucek Khailany, Sachin S. Sapatnekar
2021 Design, Automation & Test in Europe Conference & Exhibition (DATE)

2020

Opportunities for RTL and Gate Level Simulation using GPUs
Yanqing Zhang, Mark Ren, Brucek Khailany
IEEE/ACM International Conference on Computer-Aided Design (ICCAD ’20)
Accelerating Chip Design with Machine Learning
Brucek Khailany, Mark Ren, Steve Dai, Saad Godil, Ben Keller, Robert Kirby, Alicia Klinefelter, Rangharajan Venkatesan, Yanqing Zhang, Bryan Catanzaro, William Dally
IEEE Micro
GRANNITE: Graph Neural Network Inference for Transferable Power Estimation
Yanqing Zhang, Mark Ren, Brucek Khailany
Design Automation Conference (DAC) 2020
A 0.32–128 TOPS, Scalable Multi-Chip-Module-Based Deep Neural Network Inference Accelerator With Ground-Referenced Signaling in 16 nm
Brian Zimmer, Rangharajan Venkatesan, Yakun Sophia Shao, Jason Clemons, Matt Fojtik, Ted Jiang, Ben Keller, Alicia Klinefelter, Nathaniel Pinckney, Priyanka Raina, Stephen Tell, Yanqing Zhang, William Dally, Joel Emer, Tom Gray, Steve Keckler, Brucek Khailany
IEEE Journal of Solid-State Circuits (JSSC)
JSSC 2020 Best Paper Award
FIST: A Feature-Importance Sampling and Tree-Based Method for Automatic Design Flow Parameter Tuning
Zhiyao Xie, Guan-Qi Fang, Yu-Hung Huang, Mark Ren, Yanqing Zhang, Brucek Khailany, Shao-Yun Fang, Jiang Hu, Yiran Chen, Erick Carvajal Barboza
ASP-DAC 2020

2019

MAGNet: A Modular Accelerator Generator for Neural Networks
Rangharajan Venkatesan, Sophia Shao, Miaorong Wang, Jason Clemons, Steve Dai, Matt Fojtik, Ben Keller, Alicia Klinefelter, Nathaniel Pinckney, Priyanka Raina, Yanqing Zhang, Brian Zimmer, William Dally, Joel Emer, Steve Keckler, Brucek Khailany
International Conference On Computer Aided Design
Simba: Scaling Deep-Learning Inference withMulti-Chip-Module-Based Architecture
Sophia Shao, Jason Clemons, Rangharajan Venkatesan, Brian Zimmer, Matt Fojtik, Ted Jiang, Ben Keller, Alicia Klinefelter, Nathaniel Pinckney, Priyanka Raina, Stephen Tell, Yanqing Zhang, William Dally, Joel Emer, Tom Gray, Brucek Khailany, Steve Keckler
52nd IEEE/ACM International Symposium on Microarchitecture
MICRO52 Best Paper Award
A 0.11 pJ/Op, 0.32-128 TOPS, Scalable Multi-Chip-Module-based Deep Neural Network Accelerator Designed with a High-Productivity VLSI Methodology
Rangharajan Venkatesan, Sophia Shao, Brian Zimmer, Jason Clemons, Matt Fojtik, Ted Jiang, Ben Keller, Alicia Klinefelter, Nathaniel Pinckney, Priyanka Raina, Stephen Tell, Yanqing Zhang, William Dally, Joel Emer, Tom Gray, Steve Keckler, Brucek Khailany
Hot Chips: A Symposium on High Performance Chips
A 0.11 pJ/Op, 0.32-128 TOPS, Scalable Multi-Chip-Module-based Deep Neural Network Accelerator with Ground-Reference Signaling in 16nm
Brian Zimmer, Rangharajan Venkatesan, Sophia Shao, Jason Clemons, Matt Fojtik, Ted Jiang, Ben Keller, Alicia Klinefelter, Nathaniel Pinckney, Priyanka Raina, Stephen Tell, Yanqing Zhang, William Dally, Joel Emer, Tom Gray, Steve Keckler, Brucek Khailany
Symposium on VLSI Circuits Digest of Technical Papers
PRIMAL: Power Inference using Machine Learning
Yuan Zhou, Mark Ren, Yanqing Zhang, Ben Keller, Brucek Khailany, Zhiru Zhang
Design Automation Conference (DAC)

2018

A Modular Digital VLSI Flow for High-Productivity SoC Design
Brucek Khailany, Evgeni Krimer, Rangharajan Venkatesan, Jason Clemons, Joel Emer, Matt Fojtik, Alicia Klinefelter, Michael Pellauer, Nathaniel Pinckney, Sophia Shao, Shreesha Srinath, Christopher Torng, Sam (Likun) Xi, Yanqing Zhang, Brian Zimmer
Design Automation Conference (DAC)