A Modular Digital VLSI Flow for High-Productivity SoC Design

A high-productivity digital VLSI flow for designing complex SoCs is presented. The flow includes high-level synthesis tools, an object-oriented library of synthesizable SystemC and C++ components, and a modular VLSI physical design approach based on fine-grained globally asynchronous locally synchronous (GALS) clocking. The flow was demonstrated on a 16nm FinFET testchip targeting machine learning and computer vision.

Evgeni Krimer (NVIDIA)
Alicia Klinefelter (NVIDIA)
Sophia Shao (NVIDIA)
Shreesha Srinath (Cornell)
Christopher Torng (Cornell)
Sam (Likun) Xi (Harvard)
Publication Date: 
Sunday, June 24, 2018
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