People

Nathaniel Pinckney

Nathaniel Pinckney received his PhD from David Blaauw’s research group at the University of Michigan in 2015. His research focused on near-threshold characterization of planar and FinFET devices, and fast voltage boosting. Prior to UM he worked for two years in Sun Microsystems’ VLSI Research group (presently Oracle Labs). His undergraduate degree is from Harvey Mudd College, where he was advised by David Money Harris.

Research Area(s)
Computer Architecture
Artificial Intelligence and Machine Learning
Main Field of Interest
Circuits and VLSI Design
Google Scholar
https://scholar.google.com/citations?user=v4Nb6ooAAAAJ&hl=en

Publications

2023

VerilogEval: Evaluating Large Language Models for Verilog Code Generation
Mingjie Liu, Nathaniel Pinckney, Brucek Khailany, Mark Ren
2023 IEEE/ACM International Conference on Computer-Aided Design (ICCAD)
Late Breaking Results: Test Selection For RTL Coverage By Unsupervised Learning From Fast Functional Simulation
Rongjian Liang, Nathaniel Pinckney, Yuji Chai, Mark Ren, Brucek Khailany
60th Design Automation Conference

2021

IPA: Floorplan-Aware SystemC Interconnect Performance Modeling and Generation for HLS-based SoCs
Nathaniel Pinckney, Rangharajan Venkatesan, Ben Keller, Brucek Khailany
IEEE/ACM International Conference on Computer-Aided Design (ICCAD ’21)
Simba: scaling deep-learning inference with chiplet-based architecture
Yakun Sophia Shao, Jason Clemons, Rangharajan Venkatesan, Brian Zimmer, Matt Fojtik, Ted Jiang, Ben Keller, Alicia Klinefelter, Nathaniel Pinckney, Priyanka Raina, Stephen Tell, Yanqing Zhang, William Dally, Joel Emer, Tom Gray, Brucek Khailany, Steve Keckler
Communications of the ACM
ACM Research Highlight
Verifying High-Level Latency-Insensitive Designs with Formal Model Checking
Steve Dai, Alicia Klinefelter, Mark Ren, Rangharajan Venkatesan, Ben Keller, Nathaniel Pinckney, Brucek Khailany
arXiv

2020

A 0.32–128 TOPS, Scalable Multi-Chip-Module-Based Deep Neural Network Inference Accelerator With Ground-Referenced Signaling in 16 nm
Brian Zimmer, Rangharajan Venkatesan, Yakun Sophia Shao, Jason Clemons, Matt Fojtik, Ted Jiang, Ben Keller, Alicia Klinefelter, Nathaniel Pinckney, Priyanka Raina, Stephen Tell, Yanqing Zhang, William Dally, Joel Emer, Tom Gray, Steve Keckler, Brucek Khailany
IEEE Journal of Solid-State Circuits (JSSC)
JSSC 2020 Best Paper award

2019

MAGNet: A Modular Accelerator Generator for Neural Networks
Rangharajan Venkatesan, Sophia Shao, Miaorong Wang, Jason Clemons, Steve Dai, Matt Fojtik, Ben Keller, Alicia Klinefelter, Nathaniel Pinckney, Priyanka Raina, Yanqing Zhang, Brian Zimmer, William Dally, Joel Emer, Steve Keckler, Brucek Khailany
International Conference On Computer Aided Design (ICCAD)
Simba: Scaling Deep-Learning Inference with Multi-Chip-Module-Based Architecture
Sophia Shao, Jason Clemons, Rangharajan Venkatesan, Brian Zimmer, Matt Fojtik, Ted Jiang, Ben Keller, Alicia Klinefelter, Nathaniel Pinckney, Priyanka Raina, Stephen Tell, Yanqing Zhang, William Dally, Joel Emer, Tom Gray, Brucek Khailany, Steve Keckler
International Symposium on Microarchitecture (MICRO)
Best Paper award, IEEE Micro Top Picks in Computer Architecture (Honorable Mention)
A 0.11 pJ/Op, 0.32-128 TOPS, Scalable Multi-Chip-Module-based Deep Neural Network Accelerator Designed with a High-Productivity VLSI Methodology
Rangharajan Venkatesan, Sophia Shao, Brian Zimmer, Jason Clemons, Matt Fojtik, Ted Jiang, Ben Keller, Alicia Klinefelter, Nathaniel Pinckney, Priyanka Raina, Stephen Tell, Yanqing Zhang, William Dally, Joel Emer, Tom Gray, Steve Keckler, Brucek Khailany
Hot Chips: A Symposium on High Performance Chips
A 0.11 pJ/Op, 0.32-128 TOPS, Scalable Multi-Chip-Module-based Deep Neural Network Accelerator with Ground-Reference Signaling in 16nm
Brian Zimmer, Rangharajan Venkatesan, Sophia Shao, Jason Clemons, Matt Fojtik, Ted Jiang, Ben Keller, Alicia Klinefelter, Nathaniel Pinckney, Priyanka Raina, Stephen Tell, Yanqing Zhang, William Dally, Joel Emer, Tom Gray, Steve Keckler, Brucek Khailany
Symposium on VLSI Circuits
A Fine-Grained GALS SoC with Pausible Adaptive Clocking in 16 nm FinFET
Matt Fojtik, Ben Keller, Alicia Klinefelter, Nathaniel Pinckney, Stephen Tell, Brian Zimmer, Tezaswi Raja, Kevin Zhou, William Dally, Brucek Khailany
ASYNC 2019
ASYNC 2019 Best Paper Award

2018

A Modular Digital VLSI Flow for High-Productivity SoC Design
Brucek Khailany, Evgeni Krimer, Rangharajan Venkatesan, Jason Clemons, Joel Emer, Matt Fojtik, Alicia Klinefelter, Michael Pellauer, Nathaniel Pinckney, Sophia Shao, Shreesha Srinath, Christopher Torng, Sam (Likun) Xi, Yanqing Zhang, Brian Zimmer
Design Automation Conference (DAC)