Yoshi Nishi joined NVIDIA Research in 2020 after 9+ years as a member of the NVIDIA mixed signal IO design group. Since 2013 he has led one of the design teams and successfully delivered TX and RX macros for NVLINK 1 and 2 and the PLL macro for NVLINK 3. Prior to NVIDIA he was chief architect of a 10Gbps burst-mode CDR for 10G-EPON applications at K-micro, first in the market in 2009, and chief designer of the 50Gbps InP HEMT logic family at NTT which were the first 50Gbps chips in the market in 2001. He received the B.S. and M.S. degrees in low-temperature physics from Waseda University in Tokyo, Japan.
