Ted Jiang | Research

Ted Jiang

Ted Jiang joined NVIDIA research at the end of 2012 after completing his PhD in electrical engineering at Stanford University. His research interests span a wide range of interconnection networks topics from routing algorithms, congestion control mechanisms, allocator designs, router designs, topology analysis, and network simulation. His network expertise spans from network-on-chip for SoC or CMP systems to large scale system area networks for high performance computing and Datacenters.

Research Area(s)

High Performance Computing

Google Scholar

https://scholar.google.com/citations?user=NrVDLbgAAAAJ&hl=en

Publications

2021

Simba: scaling deep-learning inference with chiplet-based architecture

Yakun Sophia Shao, Jason Clemons, Rangharajan Venkatesan, Brian Zimmer, Matt Fojtik, Ted Jiang, Ben Keller, Alicia Klinefelter, Nathaniel Pinckney, Priyanka Raina, Stephen Tell, Yanqing Zhang, William Dally, Joel Emer, Tom Gray, Brucek Khailany, Steve Keckler

Communications of the ACM

ACM Research Highlight

Need for Speed: Experiences Building a Trustworthy System-Level GPU Simulator.

Oreste Villa, Daniel Lustig, Zi Yan, Evgeny Bolotin, Yaosheng Fu, Niladrish Chatterjee, Ted Jiang, David Nellans

International Symposium on High Performance Computer Architecture (HPCA)

2020

An In-Network Architecture for Accelerating Shared-Memory Multiprocessor Collectives

Benjamin Klenk, Ted Jiang, Greg Thorson, Larry Dennison

International Symposium on Computer Architecture (ISCA)

A 0.32–128 TOPS, Scalable Multi-Chip-Module-Based Deep Neural Network Inference Accelerator With Ground-Referenced Signaling in 16 nm

Brian Zimmer, Rangharajan Venkatesan, Yakun Sophia Shao, Jason Clemons, Matt Fojtik, Ted Jiang, Ben Keller, Alicia Klinefelter, Nathaniel Pinckney, Priyanka Raina, Stephen Tell, Yanqing Zhang, William Dally, Joel Emer, Tom Gray, Steve Keckler, Brucek Khailany

IEEE Journal of Solid-State Circuits (JSSC)

JSSC 2020 Best Paper award

2019

Simba: Scaling Deep-Learning Inference with Multi-Chip-Module-Based Architecture

Sophia Shao, Jason Clemons, Rangharajan Venkatesan, Brian Zimmer, Matt Fojtik, Ted Jiang, Ben Keller, Alicia Klinefelter, Nathaniel Pinckney, Priyanka Raina, Stephen Tell, Yanqing Zhang, William Dally, Joel Emer, Tom Gray, Brucek Khailany, Steve Keckler

International Symposium on Microarchitecture (MICRO)

Best Paper award, IEEE Micro Top Picks in Computer Architecture (Honorable Mention)

A 0.11 pJ/Op, 0.32-128 TOPS, Scalable Multi-Chip-Module-based Deep Neural Network Accelerator Designed with a High-Productivity VLSI Methodology

Rangharajan Venkatesan, Sophia Shao, Brian Zimmer, Jason Clemons, Matt Fojtik, Ted Jiang, Ben Keller, Alicia Klinefelter, Nathaniel Pinckney, Priyanka Raina, Stephen Tell, Yanqing Zhang, William Dally, Joel Emer, Tom Gray, Steve Keckler, Brucek Khailany

Hot Chips: A Symposium on High Performance Chips

A 0.11 pJ/Op, 0.32-128 TOPS, Scalable Multi-Chip-Module-based Deep Neural Network Accelerator with Ground-Reference Signaling in 16nm

Brian Zimmer, Rangharajan Venkatesan, Sophia Shao, Jason Clemons, Matt Fojtik, Ted Jiang, Ben Keller, Alicia Klinefelter, Nathaniel Pinckney, Priyanka Raina, Stephen Tell, Yanqing Zhang, William Dally, Joel Emer, Tom Gray, Steve Keckler, Brucek Khailany

Symposium on VLSI Circuits

2018

Exploiting Idle Resources in a High-Radix Switch for Supplemental Storage

Matthias Blumrich, Ted Jiang, Larry Dennison

Proceedings of the International Conference for High Performance Computing, Net…

2015

Network Endpoint Congestion Control for Fine-Grained Communication

Ted Jiang, Larry Dennison, William Dally