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Computer Architecture

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2018

Optimizing Software-Directed Instruction Replication for GPU Error Detection

Abdulrahman Mahmoud, Siva Hari, Michael B. Sullivan, Timothy Tsai, Steve Keckler

Exploiting Idle Resources in a High-Radix Switch for Supplemental Storage

Matthias Blumrich, Ted Jiang, Larry Dennison

PipeProof: Automated Memory Consistency Proofs for Microarchitectural Specifications

Yatin A. Manerkar, Daniel Lustig, Margaret Martonosi, Aarti Gupta

IEEE Micro Top Picks in Computer Architecture (Honorable Mention)
Best Paper nominee

SwapCodes: Error Codes for Hardware-Software Cooperative GPU Pipeline Error Detection

Michael B. Sullivan, Siva Hari, Brian Zimmer, Timothy Tsai, Stephen W. Keckler

Harmonizing Speculative and Non-Speculative Execution in Architectures for Ordered Parallelism

Mark C. Jeffrey, Victor A. Ying, Suvinay Subramanian, Hyun Ryong Lee, Joel Emer, Daniel Sanchez

DAWG: A Defense Against Cache Timing Attacks in Speculative Execution Processors

Vladimir Kiriansky, Ilia Lebedev, Saman Amarasinghe, Srinivas Devadas, Joel Emer

CheckMate: Automated Synthesis of Hardware Exploits and Security Litmus Tests

Caroline Trippel, Daniel Lustig, Margaret Martonosi

IEEE Micro Top Picks in Computer Architecture

Combining HW/SW Mechanisms to Improve NUMA Performance of Multi-GPU Systems

Vinson Young, Aamer Jaleel, Evgeny Bolotin, Eiman Ebrahimi, David Nellans, Oreste Villa

Exposing Memory Access Patterns to Improve Instruction and Memory Efficiency in GPUs

Neal Crago, Mark Stephenson, Steve Keckler

Software-Directed Techniques for Improved GPU Register File Utilization

Dani Voitsechov, Arslan Zulfiqar, Mark Stephenson, Mark Gebhart, Steve Keckler

What Your DRAM Power Models Are Not Telling You: Lessons from a Detailed Experimental Study

Saugata Ghose, Abdullah Giray Yağlıkçı, Raghav Gupta, Donghyuk Lee, Kais Kudrolli, William X. Liu, Hasan Hassan, Kevin K. Chang, Niladrish Chatterjee, Aditya Agrawal, Mike O'Connor, Onur Mutlu

Modeling Soft Error Propagation in Programs

Guanpeng Li, Karthik Pattabiraman, Siva Hari, Michael B. Sullivan, Timothy Tsai

A Modular Digital VLSI Flow for High-Productivity SoC Design

Brucek Khailany, Evgeni Krimer, Rangharajan Venkatesan, Jason Clemons, Joel Emer, Matt Fojtik, Alicia Klinefelter, Michael Pellauer, Nathaniel Pinckney, Sophia Shao, Shreesha Srinath, Christopher Torng, Sam (Likun) Xi, Yanqing Zhang, Brian Zimmer

What Your DRAM Power Models Aren’t Telling You: Lessons from a Detailed Experimental Study

Saugata Ghose, Abdullah Giray Yağlıkçı, Raghav Gupta, Donghyuk Lee, Kais Kudrolli, William X. Liu, Hasan Hassan, Kevin Chang, Niladrish Chatterjee, Aditya Agrawal, Mike O'Connor, Onur Mutlu

A Case for Richer Cross-layer Abstractions: Bridging the Semantic Gap to Enhance Memory Optimization

Nandita Vijaykumar, Abhilasha Jain, Diptesh Majumdar, Kevin Hsieh, Gennady Pekhimenko, Eiman Ebrahimi, Nastaran Hajinazar, Phillip B. Gibbons, Onur Mutlu

The Locality Descriptor: A Holistic Cross-Layer Abstraction to Express Data Locality in GPUs

Nandita Vijayumar, Eiman Ebrahimi, Kevin Hsieh, Phillip B. Gibbons, Onur Mutlu

UCNN: Exploiting Computational Reuse in Deep Neural Networks via Weight Repetition

Kartik Hegde, Jiyong Yu, Rohit Agrawal, Mengjia Yan, Michael Pellauer, Christopher W. Fletcher

ACCORD: Enabling Associativity for Gigascale DRAM Caches by Coordinating Way-Install and Way-Prediction

Vinson Young, Chiachen Chou, Aamer Jaleel, Moinuddin Qureshi

Full-Stack Memory Model Verification with TriCheck

Caroline Trippel, Yatin A. Manerkar, Daniel Lustig, Michael Pellauer, Margaret Martonosi

Voltron: Understanding and Exploiting the Voltage-Latency-Reliability Trade-Offs in Modern DRAM Chips to Improve Energy Efficiency

Kevin K. Chang, Abdullah Giray Yağlıkçı, Saugata Ghose, Aditya Agrawal, Niladrish Chatterjee, Abhijith Kashyap, Donghyuk Lee, Mike O'Connor, Hasan Hassan, Onur Mutlu

DUO: Exposing On-chip Redundancy to Rank-Level ECC for High Reliability

Seong-Lyong Gong, Jungrae Kim, Michael B. Sullivan, Howard David, Mattan Erez

Compressing DMA Engine: Leveraging Activation Sparsity for Training Deep Neural Networks

Minsoo Rhu, Mike O'Connor, Niladrish Chatterjee, Jeff Pool, Youngeun Kwon, Steve Keckler

Reducing Data Transfer Energy by Exploiting Similarity within a Data Transaction

Donghyuk Lee, Mike O'Connor, Niladrish Chatterjee

Best Paper nominee

Stitch-X: An Accelerator Architecture for Exploiting Unstructured Sparsity in Deep Neural Networks

Ching-En Lee, Yakun Sophia Shao, Jie-Fang Zhang, Angshuman Parashar, Joel Emer, Steve Keckler, Zhengya Zhang

MeltdownPrime and SpectrePrime: Automatically-Synthesized Attacks Exploiting Invalidation-Based Coherence Protocols

Caroline Trippel, Daniel Lustig, Margaret Martonosi