Publications | Research

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Circuits and VLSI Design

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2024

DRC-Coder: Automated DRC Checker Code Generation Using LLM Autonomous Agent

Chen-Chia Chang, Chia-Tung (Mark) Ho, Yaguang Li, Yiran Chen, Haoxing (Mark) Ren

VerilogCoder: Autonomous Verilog Coding Agents with Graph-based Planning and Abstract Syntax Tree (AST)-based Waveform Tracing Tool

Chia-Tung (Mark) Ho, Haoxing (Mark) Ren, Brucek Khailany

Large Language Model (LLM) for Standard Cell Layout Design Optimization

Chia-Tung (Mark) Ho, Haoxing (Mark) Ren

Best Paper Award

GL0AM: GPU Accelerated Gate Level Logic Simulator

Yanqing Zhang, Haoxing (Mark) Ren, Brucek Khailany

Learning to Compare Hardware Designs for High-Level Synthesis

Yunsheng Bai, Atefeh Sohrabizadeh, Zijian Ding, Rongjian Liang, Weikai Li, Ding Wang, Haoxing (Mark) Ren, Yizhou Sun, Jason Cong

A 0.190-pJ/bit 25.2-Gb/s/wire Inverter-Based AC-Coupled Transceiver for Short-Reach Die-to-Die Interfaces in 5-nm CMOS

Yoshinori Nishi, John W. Poulton, Xi Chen, Sanquan Song, Brian Zimmer, Walker Turner, Stephen Tell, Nikola Nedovic, John Wilson, William Dally, Tom Gray

BoolGebra: Attributed Graph-learning for Boolean Algebraic Manipulation

Yingjie Li, Anthony Agnesina, Yanqing Zhang, Haoxing (Mark) Ren, Cunxi Yu

Novel Transformer Model Based Clustering Method for Standard Cell Design Automation

Chia-Tung (Mark) Ho, Ajay Chandna, David Guan, Alvin Ho, Minsoo Kim, Yaguang Li, Haoxing (Mark) Ren

ISPD

Best Paper Award

MedPart: A Multi-Level Evolutionary Differentiable Hypergraph Partitioner

Rongjian Liang, Anthony Agnesina, Haoxing (Mark) Ren

GPU/ML-Enhanced Large Scale Global Routing Contest

Rongjian Liang, Anthony Agnesina, Wen-Hao Liu, Haoxing (Mark) Ren

2016

Snatch: Opportunistically Reassigning Power Allocation between Processor and Memory in 3D Stacks

Dimitrios Skarlatos, Renji Thomas, Aditya Agrawal, Shibin Qin, Robert Pilawa-Podgurski, Ulya R. Karpuzcu, Radu Teodorescu, Nam Sung Kim, Josep Torrellas

Hybrid Modulation for Near Zero Display Latency

Trey Greer, Josef Spjut, David Luebke, Turner Whitted

Modeling and Analysis of Power Supply Noise Tolerance with Fine-grained GALS Adaptive Clocks

Divya Akella Kamakshi, Matt Fojtik, Brucek Khailany, Sudhir Kudva, Yaping Zhou, Benton H. Calhoun

ASYNC 2016 Best Paper Award Nominee

Current parking regulator for zero droop/overshoot load transient response

Sudhir Kudva, William Dally, Trey Greer, Tom Gray

A 6.5-to-23.3fJ/b/mm Balanced Charge-Recycling Bus in 16nm FinFET CMOS at 1.7-to-2.6Gb/s/wire with Clock Forwarding and Low-Crosstalk Contraflow Wiring

John Wilson, Matt Fojtik, John Poulton, Xi Chen, Stephen Tell, Trey Greer, Tom Gray, William Dally

A 28nm 2Mbit 6T SRAM with Highly Configurable Write Assist Implementation and Capacitor Based Sense Amplifier Input Offset Compen

Mahmut Sinangil, John Poulton, Matt Fojtik, Trey Greer, Stephen Tell, Andy Gotterba, Jesse Wang, Jason Golbus, William Dally, Tom Gray