Publications

Our publications provide insight into some of our leading-edge research.

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2024

DRC-Coder: Automated DRC Checker Code Generation Using LLM Autonomous Agent
Chen-Chia Chang, Chia-Tung (Mark) Ho, Yaguang Li, Yiran Chen, Mark Haoxing Ren
VerilogCoder: Autonomous Verilog Coding Agents with Graph-based Planning and Abstract Syntax Tree (AST)-based Waveform Tracing Tool
Chia-Tung (Mark) Ho, Mark Haoxing Ren, Brucek Khailany
Large Language Model (LLM) for Standard Cell Layout Design Optimization
Chia-Tung (Mark) Ho, Mark Haoxing Ren
Best Paper Award
GL0AM: GPU Accelerated Gate Level Logic Simulator
Yanqing Zhang, Mark Haoxing Ren, Brucek Khailany
Learning to Compare Hardware Designs for High-Level Synthesis
Yunsheng Bai, Atefeh Sohrabizadeh, Zijian Ding, Rongjian Liang, Weikai Li, Ding Wang, Mark Haoxing Ren, Yizhou Sun, Jason Cong
A 0.190-pJ/bit 25.2-Gb/s/wire Inverter-Based AC-Coupled Transceiver for Short-Reach Die-to-Die Interfaces in 5-nm CMOS
Yoshinori Nishi, John W. Poulton, Xi Chen, Sanquan Song, Brian Zimmer, Walker Turner, Stephen Tell, Nikola Nedovic, John Wilson, William Dally, Tom Gray
BoolGebra: Attributed Graph-learning for Boolean Algebraic Manipulation
Yingjie Li, Anthony Agnesina, Yanqing Zhang, Mark Haoxing Ren, Cunxi Yu
Novel Transformer Model Based Clustering Method for Standard Cell Design Automation
Chia-Tung (Mark) Ho, Ajay Chandna, David Guan, Alvin Ho, Minsoo Kim, Yaguang Li, Mark Haoxing Ren
Best Paper Award
MedPart: A Multi-Level Evolutionary Differentiable Hypergraph Partitioner
Rongjian Liang, Anthony Agnesina, Mark Haoxing Ren
GPU/ML-Enhanced Large Scale Global Routing Contest
Rongjian Liang, Anthony Agnesina, Wen-Hao Liu, Mark Haoxing Ren

2019

MAGNet: A Modular Accelerator Generator for Neural Networks
Rangharajan Venkatesan, Sophia Shao, Miaorong Wang, Jason Clemons, Steve Dai, Matt Fojtik, Ben Keller, Alicia Klinefelter, Nathaniel Pinckney, Priyanka Raina, Yanqing Zhang, Brian Zimmer, William Dally, Joel Emer, Steve Keckler, Brucek Khailany
Simba: Scaling Deep-Learning Inference with Multi-Chip-Module-Based Architecture
Sophia Shao, Jason Clemons, Rangharajan Venkatesan, Brian Zimmer, Matt Fojtik, Ted Jiang, Ben Keller, Alicia Klinefelter, Nathaniel Pinckney, Priyanka Raina, Stephen Tell, Yanqing Zhang, William Dally, Joel Emer, Tom Gray, Brucek Khailany, Steve Keckler
Best Paper award
IEEE Micro Top Picks in Computer Architecture (Honorable Mention)
A 0.11 pJ/Op, 0.32-128 TOPS, Scalable Multi-Chip-Module-based Deep Neural Network Accelerator Designed with a High-Productivity VLSI Methodology
Rangharajan Venkatesan, Sophia Shao, Brian Zimmer, Jason Clemons, Matt Fojtik, Ted Jiang, Ben Keller, Alicia Klinefelter, Nathaniel Pinckney, Priyanka Raina, Stephen Tell, Yanqing Zhang, William Dally, Joel Emer, Tom Gray, Steve Keckler, Brucek Khailany
A 0.11 pJ/Op, 0.32-128 TOPS, Scalable Multi-Chip-Module-based Deep Neural Network Accelerator with Ground-Reference Signaling in 16nm
Brian Zimmer, Rangharajan Venkatesan, Sophia Shao, Jason Clemons, Matt Fojtik, Ted Jiang, Ben Keller, Alicia Klinefelter, Nathaniel Pinckney, Priyanka Raina, Stephen Tell, Yanqing Zhang, William Dally, Joel Emer, Tom Gray, Steve Keckler, Brucek Khailany
DREAMPlace: Deep Learning Toolkit-Enabled GPU Acceleration for Modern VLSI Placement
Yibo Lin, Shounak Dhar, Wuxi Li, Mark Haoxing Ren, Brucek Khailany, David Z. Pan
DAC 2019 Best Paper Award
High Performance Graph Convolutional Networks with Applications in Testability Analysis
Yuzhe Ma, Mark Haoxing Ren, Brucek Khailany, Harbinder Sikka, Lijuan Luo, Karthikeyan Natarajan, Bei Yu
PRIMAL: Power Inference using Machine Learning
Yuan Zhou, Mark Haoxing Ren, Yanqing Zhang, Ben Keller, Brucek Khailany, Zhiru Zhang
Analog/Mixed-Signal Hardware Error Modeling for Deep Learning Inference
Angad S. Rekhi, Brian Zimmer, Nikola Nedovic, Nigxi Liu, Rangharajan Venkatesan, Miaorong Wang, Brucek Khailany, William Dally, Tom Gray
A Fine-Grained GALS SoC with Pausible Adaptive Clocking in 16 nm FinFET
Matt Fojtik, Ben Keller, Alicia Klinefelter, Nathaniel Pinckney, Stephen Tell, Brian Zimmer, Tezaswi Raja, Kevin Zhou, William Dally, Brucek Khailany
ASYNC 2019 Best Paper Award
Voltage-Follower Coupling Quadrature Oscillator with Embedded Phase-Interpolator in 16nm FinFET
Xi Chen, Sanquan Song, John Poulton, Nikola Nedovic, Brian Zimmer, Stephen Tell, Tom Gray
Routability-Driven Macro Placement with Embedded CNN-Based Prediction Model
Yu-Hung Huang, Zhiyao Xie, Guan-Qi Fang, Tao-Chun Yu, Mark Haoxing Ren, Shao-Yun Fang, Yiran Chen, Jiang Hu
A 1.17-pJ/b, 25-Gb/s/pin Ground-Referenced Single-Ended Serial Link for Off- and On-Package Communication Using a Process- and Temperature-Adaptive Voltage Regulator
John Poulton, John Wilson, Walker Turner, Brian Zimmer, Xi Chen, Sudhir Kudva, Sanquan Song, Stephen Tell, Nikola Nedovic, Wenxu Zhao, Sunil Sudhakaran, Tom Gray, William Dally