Publications

Our publications provide insight into some of our leading-edge research.

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2022

HEAT: Hardware-Efficient Automatic Tensor Decomposition for Transformer Compression
Jiaqi Gu, Ben Keller, Jean Kossaifi, Anima Anandkumar, Brucek Khailany, David Z. Pan
Spotlight Paper
LNS-Madam: Low-Precision Training in Logarithmic Number System Using Multiplicative Weight Update
Jiawei Zhao, Steve Dai, Rangharajan Venkatesan, Brian Zimmer, Mustafa Ali, Ming-Yu Liu, Brucek Khailany, William Dally, Anima Anandkumar
Towards Precision-Aware Fault Tolerance Approaches for Mixed-Precision Applications
Bo Fang, Siva Hari, Timothy Tsai, Xinyi Li, Ganesh Gopalakrishnan, Ignacio Laguna, Kevin Barker, Ang Li
The Implications of Page Size Management on Graph Analytics
Aninda Manocha, Zi Yan, Esin Tureci, Juan Luis Aragón, David Nellans, Margaret Martonosi
Demystifying Map Space Exploration for NPUs
Sheng-Chun Kao, Angshuman Parashar, Po-An Tsai, Tushar Krishna
Sparseloop: An Analytical Approach to Sparse Tensor Accelerator Modeling
Yannan Nellie Wu, Po-An Tsai, Angshuman Parashar, Vivienne Sze, Joel Emer
Distinguished Artifact award
SEC-BADAEC: An Efficient ECC With No Vacancy for Strong Memory Protection
Yuseok Song, Sangjae Park, Michael B. Sullivan, Jungrae Kim
Self Adaptive Reconfigurable Arrays (SARA): Learning Flexible GEMM Accelerator Configuration and Mapping-space using ML
Ananda Samajdar, Eric Qin, Michael Pellauer, Tushar Krishna
Zhuyi: Perception Processing Rate Estimation for Safety in Autonomous Vehicles
Yu-Shun Hsiao, Siva Hari, Michał Filipiuk, Timothy Tsai, Michael B. Sullivan, Vijay Janapa Reddi, Vasu Singh, Steve Keckler
Exploiting Temporal Data Diversity for Detecting Safety-critical Faults in AV Compute Systems
Saurabh Jha, Shengkun Cui, Timothy Tsai, Siva Hari, Michael B. Sullivan, Zbigniew T. Kalbarczyk, Steve Keckler, Ravishankar K. Iyer
Ruby: Improving Hardware Efficiency for Tensor Algebra Accelerators Through Imperfect Factorization
Mark Horeni, Pooria Taheri, Po-An Tsai, Angshuman Parashar, Joel Emer, Siddharth Joshi
Mixed-Proxy Extensions for the NVIDIA PTX Memory Consistency Model
Daniel Lustig, Simon Cooksey, Olivier Giroux
IEEE Micro Top Picks in Computer Architecture (Honorable Mention)
SIMD^2: A Generalized Matrix Instruction Set for Accelerating Tensor Computation beyond GEMM
Yunan Zhang, Po-An Tsai, Hung-Wei Tseng
A Formalism of DNN Accelerator Flexibility
Sheng-Chun Kao, Hyoukjun Kwon, Michael Pellauer, Angshuman Parashar, Tushar Krishna
Learning A Continuous and Reconstructible Latent Space for Hardware Accelerator Design
Qijing Jenny Huang, Charles Hong, John Wawrzynek, Mahesh Subedar, Yakun Sophia Shao
Zhuyi: Perception Processing Rate Estimation for Safety in Autonomous Vehicles
Yu-Shun Hsiao, Siva Hari, Michał Filipiuk, Timothy Tsai, Michael B. Sullivan, Vijay Janapa Reddi, Vasu Singh, Steve Keckler
Saving PAM4 Bus Energy with SMOREs: Sparse Multi-level Opportunistic Restricted Encodings
Mike O'Connor, Donghyuk Lee, Niladrish Chatterjee, Michael B. Sullivan, Steve Keckler
Improving Locality of Irregular Updates with Hardware Assisted Propagation Blocking
Vignesh Balaji, Brandon Lucia
Best Paper nominee
Characterizing and Mitigating Soft Errors in GPU DRAM
Michael B. Sullivan, Nirmal R. Saxena, Mike O'Connor, Donghyuk Lee, Paul Racunas, Saurabh Hukerikar, Timothy Tsai, Siva Kumar Sastry Hari, Stephen W. Keckler
DiGamma: Domain-aware Genetic Algorithm for HW-Mapping Co-optimization for DNN Accelerators
Sheng-Chun Kao, Michael Pellauer, Angshuman Parashar, Tushar Krishna
Marvel: A Data-Centric Approach for Mapping Deep Learning Operators on Spatial Accelerators
Prasanth Chatarasi, Hyoukjun Kwon, Angshuman Parashar, Michael Pellauer, Tushar Krishna, Vivek Sarkar
DAGguise: Mitigating Memory Timing Side Channels
Peter W. Deutsch, Yuheng Yang, Thomas Bourgeat, Jules Drean, Joel Emer, Mengjia Yan
Accelerators
Steve Keckler, Dejan Milojicic
GPU Subwarp Interleaving
Sana Damani, Mark Stephenson, Ram Rangan, Daniel Johnson, Rishkul Kulkarni, Steve Keckler

2016

Counterexamples and Proof Loophole for the C/C++ to POWER and ARMv7 Trailing-Sync Compiler Mappings
Yatin A. Manerkar, Caroline Trippel, Daniel Lustig, Michael Pellauer, Margaret Martonosi
Snatch: Opportunistically Reassigning Power Allocation between Processor and Memory in 3D Stacks
Dimitrios Skarlatos, Renji Thomas, Aditya Agrawal, Shibin Qin, Robert Pilawa-Podgurski, Ulya R. Karpuzcu, Radu Teodorescu, Nam Sung Kim, Josep Torrellas
CANDY: Enabling Coherent DRAM Caches for Multi-Node Systems
Chiachen Chou, Aamer Jaleel, Moinuddin Qureshi
Co-Designing Accelerators and SoC Interfaces Using gem5-Aladdin
Yakun Sophia Zhao, Sam (Likun) Xi, Vijayalakshmi Srinivasan, Gu-Yeon Wei, David Brooks
Data-Centric Execution of Speculative Parallel Programs
Mark C. Jeffrey, Suvinay Subramanian, Maleen Abeydeera, Joel Emer, Daniel Sanchez
A Patch Memory System For Image Processing and Computer Vision.
Jason Clemons, Chih-Chi Cheng, Iuri Frosio, Daniel Johnson, Steve Keckler
vDNN: Virtualized Deep Neural Networks for Scalable, Memory-Efficient Neural Network Design.
Minsoo Rhu, Natalia Gimelshein, Jason Clemons, Arslan Zulfiqar, Steve Keckler
The Bunker Cache for Spatio-Value Approximation
Joshua San Miguel, Jorge Albericio, Aamer Jaleel, Natalie Enright Jerger