Publications | Research

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Circuits and VLSI Design

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2024

DRC-Coder: Automated DRC Checker Code Generation Using LLM Autonomous Agent

Chen-Chia Chang, Chia-Tung (Mark) Ho, Yaguang Li, Yiran Chen, Haoxing (Mark) Ren

VerilogCoder: Autonomous Verilog Coding Agents with Graph-based Planning and Abstract Syntax Tree (AST)-based Waveform Tracing Tool

Chia-Tung (Mark) Ho, Haoxing (Mark) Ren, Brucek Khailany

Large Language Model (LLM) for Standard Cell Layout Design Optimization

Chia-Tung (Mark) Ho, Haoxing (Mark) Ren

Best Paper Award

GL0AM: GPU Accelerated Gate Level Logic Simulator

Yanqing Zhang, Haoxing (Mark) Ren, Brucek Khailany

Learning to Compare Hardware Designs for High-Level Synthesis

Yunsheng Bai, Atefeh Sohrabizadeh, Zijian Ding, Rongjian Liang, Weikai Li, Ding Wang, Haoxing (Mark) Ren, Yizhou Sun, Jason Cong

A 0.190-pJ/bit 25.2-Gb/s/wire Inverter-Based AC-Coupled Transceiver for Short-Reach Die-to-Die Interfaces in 5-nm CMOS

Yoshinori Nishi, John W. Poulton, Xi Chen, Sanquan Song, Brian Zimmer, Walker Turner, Stephen Tell, Nikola Nedovic, John Wilson, William Dally, Tom Gray

BoolGebra: Attributed Graph-learning for Boolean Algebraic Manipulation

Yingjie Li, Anthony Agnesina, Yanqing Zhang, Haoxing (Mark) Ren, Cunxi Yu

Novel Transformer Model Based Clustering Method for Standard Cell Design Automation

Chia-Tung (Mark) Ho, Ajay Chandna, David Guan, Alvin Ho, Minsoo Kim, Yaguang Li, Haoxing (Mark) Ren

ISPD

Best Paper Award

MedPart: A Multi-Level Evolutionary Differentiable Hypergraph Partitioner

Rongjian Liang, Anthony Agnesina, Haoxing (Mark) Ren

GPU/ML-Enhanced Large Scale Global Routing Contest

Rongjian Liang, Anthony Agnesina, Wen-Hao Liu, Haoxing (Mark) Ren

2021

NVCell: Standard Cell Layout in Advanced Technology Nodes with Reinforcement Learning

Haoxing (Mark) Ren, Matt Fojtik, Brucek Khailany

Softermax: Hardware/Software Co-Design of an Efficient Softmax for Transformers

Jacob R. Stevens, Rangharajan Venkatesan, Steve Dai, Brucek Khailany, Anand Raghunathan

IPA: Floorplan-Aware SystemC Interconnect Performance Modeling and Generation for HLS-based SoCs

Nathaniel Pinckney, Rangharajan Venkatesan, Ben Keller, Brucek Khailany

Graph Learning-Based Arithmetic Block Identification

Zhuolun He, Ziyi Wang, Chen Bai, Haoyu Yang, Bei Yu

Simba: scaling deep-learning inference with chiplet-based architecture

Yakun Sophia Shao, Jason Clemons, Rangharajan Venkatesan, Brian Zimmer, Matt Fojtik, Ted Jiang, Ben Keller, Alicia Klinefelter, Nathaniel Pinckney, Priyanka Raina, Stephen Tell, Yanqing Zhang, William Dally, Joel Emer, Tom Gray, Brucek Khailany, Steve Keckler

ACM Research Highlight

VS-QUANT: Per-Vector Scaled Quantization for Accurate Low-Precision Neural Network Inference

Steve Dai, Rangharajan Venkatesan, Haoxing (Mark) Ren, Brian Zimmer, William Dally, Brucek Khailany

Fair and Comprehensive Benchmarking of Machine Learning Processing Chips

Geoffrey W. Burr, SukHwan Lim, Boris Murmann, Rangharajan Venkatesan, Marian Verhelst

Verifying High-Level Latency-Insensitive Designs with Formal Model Checking

Steve Dai, Alicia Klinefelter, Haoxing (Mark) Ren, Rangharajan Venkatesan, Ben Keller, Nathaniel Pinckney, Brucek Khailany

Ground-Referenced Single-Ended Signaling: Applications for High-Density Short-Haul Communication Systems

John Wilson, Walker Turner, John Poulton

Parasitic-Aware Analog Circuit Sizing with Graph Neural Networks and Bayesian Optimization

Mingjie Liu, Walker Turner, George Kokai, David Z. Pan, Brucek Khailany, Haoxing (Mark) Ren

MAVIREC: ML-Aided Vectored IR-Drop Estimation and Classification

Vidya A. Chhabria, Yanqing Zhang, Haoxing (Mark) Ren, Ben Keller, Brucek Khailany, Sachin S. Sapatnekar

Standard Cell Routing with Reinforcement Learning and Genetic Algorithm in Advanced Technology Nodes

Haoxing (Mark) Ren, Matt Fojtik