Publications

Our publications provide insight into some of our leading-edge research.

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2024

DRC-Coder: Automated DRC Checker Code Generation Using LLM Autonomous Agent
Chen-Chia Chang, Chia-Tung (Mark) Ho, Yaguang Li, Yiran Chen, Mark Haoxing Ren
VerilogCoder: Autonomous Verilog Coding Agents with Graph-based Planning and Abstract Syntax Tree (AST)-based Waveform Tracing Tool
Chia-Tung (Mark) Ho, Mark Haoxing Ren, Brucek Khailany
Large Language Model (LLM) for Standard Cell Layout Design Optimization
Chia-Tung (Mark) Ho, Mark Haoxing Ren
Best Paper Award
GL0AM: GPU Accelerated Gate Level Logic Simulator
Yanqing Zhang, Mark Haoxing Ren, Brucek Khailany
Learning to Compare Hardware Designs for High-Level Synthesis
Yunsheng Bai, Atefeh Sohrabizadeh, Zijian Ding, Rongjian Liang, Weikai Li, Ding Wang, Mark Haoxing Ren, Yizhou Sun, Jason Cong
A 0.190-pJ/bit 25.2-Gb/s/wire Inverter-Based AC-Coupled Transceiver for Short-Reach Die-to-Die Interfaces in 5-nm CMOS
Yoshinori Nishi, John W. Poulton, Xi Chen, Sanquan Song, Brian Zimmer, Walker Turner, Stephen Tell, Nikola Nedovic, John Wilson, William Dally, Tom Gray
BoolGebra: Attributed Graph-learning for Boolean Algebraic Manipulation
Yingjie Li, Anthony Agnesina, Yanqing Zhang, Mark Haoxing Ren, Cunxi Yu
Novel Transformer Model Based Clustering Method for Standard Cell Design Automation
Chia-Tung (Mark) Ho, Ajay Chandna, David Guan, Alvin Ho, Minsoo Kim, Yaguang Li, Mark Haoxing Ren
Best Paper Award
MedPart: A Multi-Level Evolutionary Differentiable Hypergraph Partitioner
Rongjian Liang, Anthony Agnesina, Mark Haoxing Ren
GPU/ML-Enhanced Large Scale Global Routing Contest
Rongjian Liang, Anthony Agnesina, Wen-Hao Liu, Mark Haoxing Ren

2022

Efficient Arithmetic Block Identification with Graph Learning and Network-flow
Ziyi Wang, Zhuolun He, Chen Bai, Haoyu Yang, Bei Yu
An Adversarial Active Sampling-based Data Augmentation Framework for Manufacturable Chip Design
Mingjie Liu, Haoyu Yang, Zongyi Li, Kumara Sastry, Saumyadip Mukhopadhyay, Selim Dogru, Anima Anandkumar, David Z. Pan, Brucek Khailany, Mark Haoxing Ren
LNS-Madam: Low-Precision Training in Logarithmic Number System Using Multiplicative Weight Update
Jiawei Zhao, Steve Dai, Rangharajan Venkatesan, Brian Zimmer, Mustafa Ali, Ming-Yu Liu, Brucek Khailany, William Dally, Anima Anandkumar
Why are Graph Neural Networks Effective for EDA Problems?
Mark Haoxing Ren, Siddhartha Nath, Yanqing Zhang, Hao Chen, Mingjie Liu
TransSizer: A Novel Transformer-Based Fast Gate Sizer
Siddhartha Nath, Geraldo Pradipta, Corey Hu, Tian Yang, Brucek Khailany, Mark Haoxing Ren
TAG: Learning Circuit Spatial Embedding from Layouts
Keren Zhu, Hao Chen, Walker Turner, George F. Kokai, Po-Hsuan Wei, David Z. Pan, Mark Haoxing Ren
Photonic Circuits for Accelerated Computing Systems
Ben Lee
XT-PRAGGMA: Crosstalk Pessimism Reduction Accessible by GPU Gate-level Simulations and Machine Learning
Vidya Chhabria, Ben Keller, Yanqing Zhang, Sandeep Vollala, Sreedhar Patty, Mark Haoxing Ren, Brucek Khailany
Placement Optimization via PPA-Directed Graph Clustering
Yi-Chen Lu, Tian Yang, Sung Kyu Lim, Mark Haoxing Ren
From RTL to CUDA: A GPU Acceleration Flow for RTL Simulation with Batch Stimulus
Dian-Lun Lin, Mark Haoxing Ren, Yanqing Zhang, Brucek Khailany, Tsung-Wei Huang
A 0.297-pJ/bit 50.4-Gb/s/wire Inverter-Based Short-Reach Simultaneous Bidirectional Transceiver for Die-to-Die Interface in 5nm CMOS
Yoshinori Nishi, John W. Poulton, Xi Chen, Sanquan Song, Brian Zimmer, Walker Turner, Stephen Tell, Nikola Nedovic, John Wilson, William Dally, Tom Gray
A 17–95.6 TOPS/W Deep Learning Inference Accelerator with Per-Vector Scaled 4-bit Quantization for Transformers in 5nm
Ben Keller, Rangharajan Venkatesan, Steve Dai, Stephen Tell, Brian Zimmer, William Dally, Tom Gray, Brucek Khailany
Saving PAM4 Bus Energy with SMOREs: Sparse Multi-level Opportunistic Restricted Encodings
Mike O'Connor, Donghyuk Lee, Niladrish Chatterjee, Michael B. Sullivan, Steve Keckler
AutoCRAFT: Layout Automation for Custom Circuits in Advanced FinFET Technologies
Hao Chen, Walker Turner, Sanquan Song, Keren Zhu, George Kokai, Brian Zimmer, Tom Gray, Brucek Khailany, Mark Haoxing Ren
Routability-Aware Placement for Advanced FinFET Analog Circuits with Satisfiability Modulo Theories
Hao Chen, Walker Turner, David Z. Pan, Mark Haoxing Ren
Generic Lithography Modeling with Dual-band Optics-Inspired Neural Networks
Haoyu Yang, Zongyi Li, Kumara Sastry, Saumyadip Mukhopadhyay, Mark Kilgard, Anima Anandkumar, Brucek Khailany, Vivek Singh, Mark Haoxing Ren
GATSPI: GPU Accelerated Gate-Level Simulation for Power Improvement
Yanqing Zhang, Mark Haoxing Ren, Akshay Sridharan, Brucek Khailany
Driving Down Link Energy and Driving Up Link Density in GPU Networks
Ben Lee
DeePattern: Layout Pattern Generation with Transforming Convolutional Auto-Encoder
Haoyu Yang, Shuhe Li, Wen Chen, Piyush Pathak, Frank Gennari, Ya-Chieh Lai, Bei Yu
Best Paper Award
Machine Learning and Algorithms: Let Us Team Up for EDA
Mark Haoxing Ren, Brucek Khailany, Matt Fojtik, Yanqing Zhang