Cris Cecka


Dr. Cris Cecka joined NVIDIA Research in 2015 to deploy his interests in developing advanced numerical algorithms and software. Previously, Cris worked at the new Institute for Applied Computational Science at Harvard University as a research scientist and lecturer, where he developed courses on parallel computing and robust software development in scientific computing. He also worked in the Mathematics Department at the Massachusetts Institute of Technology as a research associate, where he focused on developing and applying integral equation methods and generalized N-body problems via hierarchical matrix factorizations. He received his Ph.D. from Stanford University in computational and mathematical engineering in 2011.


Main Field of Interest: 

Turner Whitted

Turner Whitted joined NVIDIA in 2014 after 15 years at Microsoft Research where he founded the hardware devices group and managed the graphics group along with a variety of other groups devoted to HCI. He was a co-inventor of the signal processing algorithm for ClearTypeTM. He co-founded Numerical Design Limited in 1983 and served as president and technical director until 1996. Earlier, as a member of the technical staff at Bell Laboratories, he introduced recursive ray tracing as an implementation of global illumination. In his early career he designed digital test equipment, antenna measurement systems, and components of a sonar signal processor.

He earned BSE and MS degrees from Duke University and a PhD from North Carolina State University, all in electrical engineering. He is an adjunct research professor of Computer Science at the University of North Carolina and adjunct professor of Electrical and Computer Engineering at North Carolina State University. In the past he has served on the editorial boards of IEEE Computer Graphics and Applications and ACM Transactions on Graphics, was papers chair for SIGGRAPH 97, and served on the SIGGRAPH executive committee. He is an ACM Fellow and a member of the National Academy of Engineering

Rangharajan Venkatesan

Rangharajan Venkatesan is a Senior Research Scientist in the ASIC & VLSI Research group in NVIDIA. He received the B.Tech. degree in Electronics and Communication Engineering from the Indian Institute of Technology,  Roorkee in 2009 and the Ph.D. degree in Electrical and Computer Engineering from Purdue University in August 2014. His research interests include variation-tolerant design methodologies, low power SoC design, machine learning, spintronic memories, and approximate computing. During his Ph.D., he was a recipient of Purdue’s Ross Fellowship for the year 2009–2010 and the Bilsland Dissertation Fellowship for the year 2013–2014.  His work on spintronic memory design was recognized with the Best Paper Award at the International Symposium on Low Power Electronics and Design (ISLPED), 2012 and Best paper nomination at the Design, Automation and Test in Europe (DATE), 2017.



Mike Bauer

Michael Bauer joined NVIDIA Research in October of 2014 after finishing his PhD in computer science at Stanford University.  As part of his thesis, he developed the Legion programming system for high performance supercomputing codes.  Legion is currently deployed in several production applications running on the top supercomputers in the world.  Michael was also the primary author of both the CudaDMA library and Singe DSL compiler, both of which were early examples of warp-specialized GPU programming.

Joel Emer

Dr. Joel S. Emer joined NVIDIA in 2014 and is a member of the Architecture Research group. He is also a Professor of the Practice at MIT. He is responsible for exploration of future architectures as well as modeling and analysis methodologies. Prior to joining NVIDIA he worked at Intel where he was an Intel Fellow and Director of Microarchitecture Research.  Previously he worked at Compaq and Digital Equipment Corporation.

Emer has held various research and advanced development positions investigating processor microarchitecture and developing performance modeling and evaluation techniques. He has made architectural contributions to a number of VAX, Alpha and X86 processors and is recognized as one of the developers of the widely employed quantitative approach to processor performance evaluation. More recently, he has been recognized for his contributions in the advancement of simultaneous multithreading technology, processor reliability analysis, cache organization and spatial architectures.

Emer received a bachelor's degree with highest honors in electrical engineering in 1974, and his master's degree in 1975 -- both from Purdue University. He earned a doctorate in electrical engineering from the University of Illinois in 1979. Emer has received numerous public recognitions, including being named a Fellow of both the ACM and IEEE, and he was the 2009 recipient of the Eckert-Mauchly award for lifetime contributions in computer architecture.

Arslan Zulfiqar

Arslan Zulfiqar joined NVIDIA research in 2014. His primary research interests are in the area of processor architecture and interconnection networks. Arslan has a B.S. in electrical engineering from the University of Illinois (Urbana-Champaign) and a Ph.D. from the University of Wisconsin (Madison) also in electrical engineering.

Steven Dalton

Steven Dalton joined NVIDIA Research in July 2014. He completed his Ph.D. in computer science at UIUC, where his research focused on mapping irregular operations on sparse matrices related to algebraic multigrid (AMG) methods to GPU architectures. Along with Nathan Bell, he was one of the primary contributors to our Cusp sparse linear algebra research library. He holds two Bachelor of Science degrees from Georgia Institute of Technology in the areas of Physics and Computer Science. He has held internships at several other organizations, including, the Federal Reserve Bank of Atlanta, Lawrence Livermore National Laboratory, and Argonne National Laboratory. He is also a 2012 recipient of the NVIDIA PhD Fellowship.


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