People

Mark Ren

Haoxing "Mark" Ren's research interest is in EDA and design methodology. He worked at IBM EDA Lab from 2000 to 2006 where he was the key developer of placement tools. He joined IBM Research DA group in 2007 where he led the development of  logic ECO synthesis tools and high level synthesis tools. Prior to joining NVIDIA Research in May 2016, he was a technical executive at PowerCore, a startup developing server-class CPUs as part of the IBM OpenPower initiative.  Mark earned a PhD degree in Computer Engineering from University of Texas at Austin, a M.S. degree in Computer Engineering from Rensselaer Polytechnic Institute, and a B.S. degree in Electrical Engineering from Shanghai Jiao Tong University.

Research Area(s)
Artificial Intelligence and Machine Learning
Circuits and VLSI Design
Google Scholar
https://scholar.google.com/citations?view_op=list_works&hl=en&user=y-TNUJ4AAAAJ…

Publications

2023

DREAM-GAN: Advancing DREAMPlace towards Commercial-Quality using Generative Adversarial Learning
Yi-Chen Lu, Haoxing (Mark) Ren, Hao-Hsiang Hsiao, Sung Kyu Lim
International Symposium on Physical Design 2023
NVCell 2: Routability-Driven Standard Cell Layout in Advanced Nodes with Lattice Graph Routability Model
Chia-Tung (Mark) Ho, Alvin Ho, Matt Fojtik, Minsoo Kim, Shang Wei, Yaguang LI, Brucek Khailany, Haoxing (Mark) Ren
International Symposium on Physical Design 2023
Reinforcement Learning Guided Detailed Routing for Custom Circuits
Hao Chen, Kai-Chieh Hsu, Walker Turner, Po-Hsuan Wei, Keren Zhu, David Z. Pan, Haoxing (Mark) Ren
International Symposium on Physical Design 2023
AutoDMP: Automated DREAMPlace-based Macro Placement
Anthony Agnesina, Puranjay Rajvanshi, Tian Yang, Geraldo Pradipta, Austin Jiao, Ben Keller, Brucek Khailany, Haoxing (Mark) Ren
International Symposium on Physical Design 2023
Enabling Scalable AI Computational Lithography with Physics-Inspired Models
Haoyu Yang, Mark Ren
2023 28th Asia and South Pacific Design Automation Conference (ASP-DAC)
BufFormer: A Generative ML Framework for Scalable Buffering
Rongjian Liang, Siddhartha Nath, Anand Rajaram, Jiang Hu, Mark Ren
28th Asia and South Pacific Design Automation Conference

2022

An Adversarial Active Sampling-based Data Augmentation Framework for Manufacturable Chip Design
Mingjie Liu, Haoyu Yang, Zongyi Li, Kumara Sastry, Saumyadip Mukhopadhyay, Selim Dogru, Anima Anandkumar, David Z. Pan, Brucek Khailany, Mark Ren
Workshop on ML for Systems at NeurIPS
TAG: Learning Circuit Spatial Embedding from Layouts
Keren Zhu, Hao Chen, Walker Turner, George F. Kokai, Po-Hsuan Wei, David Z. Pan, Mark Ren
2022 International Conference on Computer-Aided Design
Why are Graph Neural Networks Effective for EDA Problems?
Mark Ren, Siddhartha Nath, Yanqing Zhang, Hao Chen, Mingjie Liu
2022 International Conference on Computer-Aided Design
TransSizer: A Novel Transformer-Based Fast Gate Sizer
Siddhartha Nath, Geraldo Pradipta, Corey Hu, Tian Yang, Brucek Khailany, Mark Ren
2022 International Conference on Computer-Aided Design
XT-PRAGGMA: Crosstalk Pessimism Reduction Accessible by GPU Gate-level Simulations and Machine Learning
Vidya Chhabria, Ben Keller, Yanqing Zhang, Sandeep Vollala, Sreedhar Patty, Mark Ren, Brucek Khailany
MLCAD '22: Proceedings of the 2022 ACM/IEEE Workshop on Machine Learning for CAD
Placement Optimization via PPA-Directed Graph Clustering
Yi-Chen Lu, Tian Yang, Sung Kyu Lim, Mark Ren
MLCAD '22: Proceedings of the 2022 ACM/IEEE Workshop on Machine Learning for CAD
From RTL to CUDA: A GPU Acceleration Flow for RTL Simulation with Batch Stimulus
Dian-Lun Lin, Mark Ren, Yanqing Zhang, Brucek Khailany, Tsung-Wei Huang
51st International Conference on Parallel Processing (ICPP '22)
AutoCRAFT: Layout Automation for Custom Circuits in Advanced FinFET Technologies
Hao Chen, Walker Turner, Sanquan Song, Keren Zhu, George Kokai, Brian Zimmer, Tom Gray, Brucek Khailany, Mark Ren
International Symposium on Physical Design 2022
Routability-Aware Placement for Advanced FinFET Analog Circuits with Satisfiability Modulo Theories
Hao Chen, Walker Turner, David Z. Pan, Mark Ren
Design, Automation & Test in Europe 2022
Generic Lithography Modeling with Dual-band Optics-Inspired Neural Networks
Haoyu Yang, Zongyi Li, Kumara Sastry, Saumyadip Mukhopadhyay, Mark Kilgard, Anima Anandkumar, Brucek Khailany, Vivek Singh, Mark Ren
2022 Design Automation Conference
GATSPI: GPU Accelerated Gate-Level Simulation for Power Improvement
Yanqing Zhang, Mark Ren, Akshay Sridharan, Brucek Khailany
2022 Design Automation Conference
Machine Learning and Algorithms: Let Us Team Up for EDA
Mark Ren, Brucek Khailany, Matt Fojtik, Yanqing Zhang
IEEE Design & Test

2021

NVCell: Standard Cell Layout in Advanced Technology Nodes with Reinforcement Learning
Mark Ren, Matt Fojtik, Brucek Khailany
Design Automation Conference (DAC) 2021 (Invited special session paper)
VS-QUANT: Per-Vector Scaled Quantization for Accurate Low-Precision Neural Network Inference
Steve Dai, Rangharajan Venkatesan, Mark Ren, Brian Zimmer, William Dally, Brucek Khailany
MLSys 2021
Verifying High-Level Latency-Insensitive Designs with Formal Model Checking
Steve Dai, Alicia Klinefelter, Mark Ren, Rangharajan Venkatesan, Ben Keller, Nathaniel Pinckney, Brucek Khailany
arXiv
MAVIREC: ML-Aided Vectored IR-Drop Estimation and Classification
Vidya A. Chhabria, Yanqing Zhang, Mark Ren, Ben Keller, Brucek Khailany, Sachin S. Sapatnekar
2021 Design, Automation & Test in Europe Conference & Exhibition (DATE)
Parasitic-Aware Analog Circuit Sizing with Graph Neural Networks and Bayesian Optimization
Mingjie Liu, Walker Turner, George Kokai, David Z. Pan, Brucek Khailany, Mark Ren
2021 Design, Automation & Test in Europe Conference & Exhibition (DATE)
Standard Cell Routing with Reinforcement Learning and Genetic Algorithm in Advanced Technology Nodes
Mark Ren, Matt Fojtik
26th Asia and South Pacific Design Automation Conference (ASP-DAC) 2021

2020

NVCell: Generate Standard Cell Layout in Advanced Technology Nodes with Reinforcement Learning
Mark Ren, Matt Fojtik, Brucek Khailany
Workshop on ML for Systems at NeurIPS
Opportunities for RTL and Gate Level Simulation using GPUs
Yanqing Zhang, Mark Ren, Brucek Khailany
IEEE/ACM International Conference on Computer-Aided Design (ICCAD ’20)
Accelerating Chip Design with Machine Learning
Brucek Khailany, Mark Ren, Steve Dai, Saad Godil, Ben Keller, Robert Kirby, Alicia Klinefelter, Rangharajan Venkatesan, Yanqing Zhang, Bryan Catanzaro, William Dally
IEEE Micro
ParaGraph: Layout Parasitics and Device Parameter Prediction using Graph Neural Networks
Mark Ren, George Kokai, Walker Turner, Ting-Sheng Ku
Design Automation Conference (DAC) 2020
GRANNITE: Graph Neural Network Inference for Transferable Power Estimation
Yanqing Zhang, Mark Ren, Brucek Khailany
Design Automation Conference (DAC) 2020
DREAMPlace: Deep Learning Toolkit-Enabled GPU Acceleration for Modern VLSI Placement
Yibo Lin, Zixuan Jiang, Jiaqi Gu, Wuxi Li, Shounak Dhar, Mark Ren, Brucek Khailany, David Z. Pan
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (…
2021 IEEE Transactions on Computer-Aided Design Donald O. Pederson Best Paper Award
ABCDPlace: Accelerated Batch-based Concurrent Detailed Placement on Multi-threaded CPUs and GPUs
Yibo Lin, Wuxi Li, Jiaqi Gu, Mark Ren, Brucek Khailany, David Z. Pan
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (…
FIST: A Feature-Importance Sampling and Tree-Based Method for Automatic Design Flow Parameter Tuning
Zhiyao Xie, Guan-Qi Fang, Yu-Hung Huang, Mark Ren, Yanqing Zhang, Brucek Khailany, Shao-Yun Fang, Jiang Hu, Yiran Chen, Erick Carvajal Barboza
ASP-DAC 2020
PowerNet: Transferable Dynamic IR Drop Estimation via Maximum Convolutional Neural Network
Zhiyao Xie, Mark Ren, Brucek Khailany, Ye Sheng, Santosh Santosh, Jiang Hu, Yiran Chen
ASP-DAC 2020

2019

DREAMPlace: Deep Learning Toolkit-Enabled GPU Acceleration for Modern VLSI Placement
Yibo Lin, Shounak Dhar, Wuxi Li, Mark Ren, Brucek Khailany, David Z. Pan
Design Automation Conference (DAC) 2019
DAC 2019 Best Paper Award
High Performance Graph Convolutional Networks with Applications in Testability Analysis
Yuzhe Ma, Mark Ren, Brucek Khailany, Harbinder Sikka, Lijuan Luo, Karthikeyan Natarajan, Bei Yu
Design Automation Conference (DAC)
PRIMAL: Power Inference using Machine Learning
Yuan Zhou, Mark Ren, Yanqing Zhang, Ben Keller, Brucek Khailany, Zhiru Zhang
Design Automation Conference (DAC)
Routability-Driven Macro Placement with Embedded CNN-Based Prediction Model
Yu-Hung Huang, Zhiyao Xie, Guan-Qi Fang, Tao-Chun Yu, Mark Ren, Shao-Yun Fang, Yiran Chen, Jiang Hu
Design, Automation and Test in Europe

2018

RouteNet: Routability Prediction for Mixed-size Designs using Convolutional Neural Network
Zhiyao Xie, Yu-Hung Huang, Guan-Qi Fang, Mark Ren, Shao-Yun Fang, Yiran Chen, Hu Jiang
International Conference On Computer Aided Design