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Research Labs
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Circuits and VLSI Design
(107)
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(52)
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(16)
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(9)
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(7)
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107 results found
Circuits and VLSI Design
Clear all
Circuits and VLSI Design
2025
Marco: Configurable Graph-Based Task Solving and Multi-AI Agents Framework for Hardware Design
Chia-Tung (Mark) Ho
, Jing Gong,
Yunsheng Bai
,
Chenhui Deng
,
Haoxing (Mark) Ren
,
Brucek Khailany
2024
DRC-Coder: Automated DRC Checker Code Generation Using LLM Autonomous Agent
Chen-Chia Chang,
Chia-Tung (Mark) Ho
, Yaguang Li, Yiran Chen,
Haoxing (Mark) Ren
VerilogCoder: Autonomous Verilog Coding Agents with Graph-based Planning and Abstract Syntax Tree (AST)-based Waveform Tracing Tool
Chia-Tung (Mark) Ho
,
Haoxing (Mark) Ren
,
Brucek Khailany
Large Language Model (LLM) for Standard Cell Layout Design Optimization
Chia-Tung (Mark) Ho
,
Haoxing (Mark) Ren
Best Paper Award
GL0AM: GPU Accelerated Gate Level Logic Simulator
Yanqing Zhang
,
Haoxing (Mark) Ren
,
Brucek Khailany
A 0.190-pJ/bit 25.2-Gb/s/wire Inverter-Based AC-Coupled Transceiver for Short-Reach Die-to-Die Interfaces in 5-nm CMOS
Yoshinori Nishi
, John W. Poulton,
Xi Chen
,
Sanquan Song
,
Brian Zimmer
,
Walker Turner
,
Stephen Tell
,
Nikola Nedovic
,
John Wilson
,
William Dally
,
Tom Gray
BoolGebra: Attributed Graph-learning for Boolean Algebraic Manipulation
Yingjie Li, Anthony Agnesina,
Yanqing Zhang
,
Haoxing (Mark) Ren
, Cunxi Yu
Novel Transformer Model Based Clustering Method for Standard Cell Design Automation
Chia-Tung (Mark) Ho
, Ajay Chandna, David Guan, Alvin Ho, Minsoo Kim, Yaguang Li,
Haoxing (Mark) Ren
ISPD
Best Paper Award
MedPart: A Multi-Level Evolutionary Differentiable Hypergraph Partitioner
Rongjian Liang
, Anthony Agnesina,
Haoxing (Mark) Ren
GPU/ML-Enhanced Large Scale Global Routing Contest
Rongjian Liang
, Anthony Agnesina,
Wen-Hao Liu
,
Haoxing (Mark) Ren
2023
CircuitOps: An ML Infrastructure Enabling Generative AI for VLSI Circuit Optimization
Rongjian Liang
, Anthony Agnesina, Geraldo Pradipta, Vidya A. Chhabria,
Haoxing (Mark) Ren
ChipNeMo: Domain-Adapted LLMs for Chip Design
Mingjie Liu
, Teo Ene, Robert Kirby, Chris Cheng,
Nathaniel Pinckney
,
Rongjian Liang
, Jonah Alben, Himyanshu Anand, Sanmitra Banerjee, Ismet Bayraktaroglu, Bonita Bhaskaran, Bryan Catanzaro, Arjun Chaudhuri, Sharon Clay, Bill Dally, Laura Dang, Parikshit Deshpande, Siddhanth Dhodhi, Sameer Halepete, Eric Hill, Jiashang Hu, Sumit Jain,
Brucek Khailany
, George Kokai, Kishor Kunal, Xiaowei Li, Charley Lind, Hao Liu, Stuart Oberman, Sujeet Omar, Sreedhar Pratty, Jonathan Raman, Ambar Sarkar, Zhengjiang Shao, Hanfei Sun, Pratik P Suthar, Varun Tej,
Walker Turner
, Kaizhe Xu,
Haoxing (Mark) Ren
VerilogEval: Evaluating Large Language Models for Verilog Code Generation
Mingjie Liu
,
Nathaniel Pinckney
,
Brucek Khailany
,
Haoxing (Mark) Ren
Late Breaking Results: Test Selection For RTL Coverage By Unsupervised Learning From Fast Functional Simulation
Rongjian Liang
,
Nathaniel Pinckney
, Yuji Chai,
Haoxing (Mark) Ren
,
Brucek Khailany
Efficient Transformer Inference with Statically Structured Sparse Attention
Steve Dai
, Hasan Genc,
Rangharajan Venkatesan
,
Brucek Khailany
Physics-Informed Optical Kernel Regression Using Complex-valued Neural Fields
Guojin Chen, Zehua Pei,
Haoyu Yang
, Yuzhe Ma, Bei Yu, Martin Wong
A 0.190-pJ/bit 25.2-Gb/s/wire Inverter-Based AC-Coupled Transceiver for Short-Reach Die-to-Die Interfaces in 5-nm CMOS
Yoshinori Nishi
, John W. Poulton,
Xi Chen
,
Sanquan Song
,
Brian Zimmer
,
Walker Turner
,
Stephen Tell
,
Nikola Nedovic
,
John Wilson
,
William Dally
,
Tom Gray
A 9.7fJ/Conv.-Step Capacitive Sensor Readout Circuit with Incremental Zoomed Time Domain Quantization
Zilong Shen, Xiyuan Tang, Zhongyi Wu, Haoyang Luo, Zongnan Wang,
Mingjie Liu
, Xing Zhang, Yuan Wang
A 0.297-pJ/Bit 50.4-Gb/s/Wire Inverter-Based Short-Reach Simultaneous Bi-Directional Transceiver for Die-to-Die Interface in 5-nm CMOS
Yoshinori Nishi
, John W. Poulton,
Walker Turner
,
Xi Chen
,
Sanquan Song
,
Brian Zimmer
,
Stephen Tell
,
Nikola Nedovic
,
John Wilson
,
William Dally
,
Tom Gray
Reinforcement Learning Guided Detailed Routing for Custom Circuits
Hao Chen, Kai-Chieh Hsu,
Walker Turner
, Po-Hsuan Wei, Keren Zhu, David Z. Pan,
Haoxing (Mark) Ren
ISPD
DREAM-GAN: Advancing DREAMPlace towards Commercial-Quality using Generative Adversarial Learning
Yi-Chen Lu,
Haoxing (Mark) Ren
, Hao-Hsiang Hsiao, Sung Kyu Lim
ISPD
NVCell 2: Routability-Driven Standard Cell Layout in Advanced Nodes with Lattice Graph Routability Model
Chia-Tung (Mark) Ho
, Alvin Ho,
Matt Fojtik
, Minsoo Kim, Shang Wei, Yaguang LI,
Brucek Khailany
,
Haoxing (Mark) Ren
ISPD
AutoDMP: Automated DREAMPlace-based Macro Placement
Anthony Agnesina, Puranjay Rajvanshi, Tian Yang, Geraldo Pradipta, Austin Jiao,
Ben Keller
,
Brucek Khailany
,
Haoxing (Mark) Ren
ISPD
On Legalization of Die Bonding Bumps and Pads for 3D ICs
Sai Pentapati, Anthony Agnesina, Moritz Brunion, Yen-Hsiang Huang, Sung Kyu Lim
ISPD
Enabling Scalable AI Computational Lithography with Physics-Inspired Models
Haoyu Yang
,
Haoxing (Mark) Ren
Beyond CPO: A Motivation and Approach for Bringing Optics onto the Silicon Interposer
Ben Lee
,
Nikola Nedovic
,
Trey Greer
,
Tom Gray
A 95.6-TOPS/W Deep Learning Inference Accelerator With Per-Vector Scaled 4-bit Quantization in 5 nm
Ben Keller
,
Rangharajan Venkatesan
,
Steve Dai
,
Stephen Tell
,
Brian Zimmer
,
Charbel Sakr
,
William Dally
,
Tom Gray
,
Brucek Khailany
BufFormer: A Generative ML Framework for Scalable Buffering
Rongjian Liang
, Siddhartha Nath, Anand Rajaram, Jiang Hu,
Haoxing (Mark) Ren
2022
Efficient Arithmetic Block Identification with Graph Learning and Network-flow
Ziyi Wang, Zhuolun He, Chen Bai,
Haoyu Yang
, Bei Yu
An Adversarial Active Sampling-based Data Augmentation Framework for Manufacturable Chip Design
Mingjie Liu
,
Haoyu Yang
, Zongyi Li, Kumara Sastry, Saumyadip Mukhopadhyay, Selim Dogru, Anima Anandkumar, David Z. Pan,
Brucek Khailany
,
Haoxing (Mark) Ren
NeurIPS
LNS-Madam: Low-Precision Training in Logarithmic Number System Using Multiplicative Weight Update
Jiawei Zhao,
Steve Dai
,
Rangharajan Venkatesan
,
Brian Zimmer
, Mustafa Ali,
Ming-Yu Liu
,
Brucek Khailany
,
William Dally
, Anima Anandkumar
Why are Graph Neural Networks Effective for EDA Problems?
Haoxing (Mark) Ren
, Siddhartha Nath,
Yanqing Zhang
, Hao Chen,
Mingjie Liu
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