Publications | Research

18 results found
Circuits and VLSI Design

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2021

NVCell: Standard Cell Layout in Advanced Technology Nodes with Reinforcement Learning

Haoxing (Mark) Ren, Matt Fojtik, Brucek Khailany

Softermax: Hardware/Software Co-Design of an Efficient Softmax for Transformers

Jacob R. Stevens, Rangharajan Venkatesan, Steve Dai, Brucek Khailany, Anand Raghunathan

IPA: Floorplan-Aware SystemC Interconnect Performance Modeling and Generation for HLS-based SoCs

Nathaniel Pinckney, Rangharajan Venkatesan, Ben Keller, Brucek Khailany

Graph Learning-Based Arithmetic Block Identification

Zhuolun He, Ziyi Wang, Chen Bai, Haoyu Yang, Bei Yu

Simba: scaling deep-learning inference with chiplet-based architecture

Yakun Sophia Shao, Jason Clemons, Rangharajan Venkatesan, Brian Zimmer, Matt Fojtik, Ted Jiang, Ben Keller, Alicia Klinefelter, Nathaniel Pinckney, Priyanka Raina, Stephen Tell, Yanqing Zhang, William Dally, Joel Emer, Tom Gray, Brucek Khailany, Steve Keckler

ACM Research Highlight

VS-QUANT: Per-Vector Scaled Quantization for Accurate Low-Precision Neural Network Inference

Steve Dai, Rangharajan Venkatesan, Haoxing (Mark) Ren, Brian Zimmer, William Dally, Brucek Khailany

Fair and Comprehensive Benchmarking of Machine Learning Processing Chips

Geoffrey W. Burr, SukHwan Lim, Boris Murmann, Rangharajan Venkatesan, Marian Verhelst

Verifying High-Level Latency-Insensitive Designs with Formal Model Checking

Steve Dai, Alicia Klinefelter, Haoxing (Mark) Ren, Rangharajan Venkatesan, Ben Keller, Nathaniel Pinckney, Brucek Khailany

Ground-Referenced Single-Ended Signaling: Applications for High-Density Short-Haul Communication Systems

John Wilson, Walker Turner, John Poulton

Parasitic-Aware Analog Circuit Sizing with Graph Neural Networks and Bayesian Optimization

Mingjie Liu, Walker Turner, George Kokai, David Z. Pan, Brucek Khailany, Haoxing (Mark) Ren

MAVIREC: ML-Aided Vectored IR-Drop Estimation and Classification

Vidya A. Chhabria, Yanqing Zhang, Haoxing (Mark) Ren, Ben Keller, Brucek Khailany, Sachin S. Sapatnekar

Standard Cell Routing with Reinforcement Learning and Genetic Algorithm in Advanced Technology Nodes

Haoxing (Mark) Ren, Matt Fojtik

2016

Snatch: Opportunistically Reassigning Power Allocation between Processor and Memory in 3D Stacks

Dimitrios Skarlatos, Renji Thomas, Aditya Agrawal, Shibin Qin, Robert Pilawa-Podgurski, Ulya R. Karpuzcu, Radu Teodorescu, Nam Sung Kim, Josep Torrellas

Hybrid Modulation for Near Zero Display Latency

Trey Greer, Josef Spjut, David Luebke, Turner Whitted

Modeling and Analysis of Power Supply Noise Tolerance with Fine-grained GALS Adaptive Clocks

Divya Akella Kamakshi, Matt Fojtik, Brucek Khailany, Sudhir Kudva, Yaping Zhou, Benton H. Calhoun

ASYNC 2016 Best Paper Award Nominee

Current parking regulator for zero droop/overshoot load transient response

Sudhir Kudva, William Dally, Trey Greer, Tom Gray

A 6.5-to-23.3fJ/b/mm Balanced Charge-Recycling Bus in 16nm FinFET CMOS at 1.7-to-2.6Gb/s/wire with Clock Forwarding and Low-Crosstalk Contraflow Wiring

John Wilson, Matt Fojtik, John Poulton, Xi Chen, Stephen Tell, Trey Greer, Tom Gray, William Dally

A 28nm 2Mbit 6T SRAM with Highly Configurable Write Assist Implementation and Capacitor Based Sense Amplifier Input Offset Compen

Mahmut Sinangil, John Poulton, Matt Fojtik, Trey Greer, Stephen Tell, Andy Gotterba, Jesse Wang, Jason Golbus, William Dally, Tom Gray