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Circuits and VLSI Design

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2022

Efficient Arithmetic Block Identification with Graph Learning and Network-flow

Ziyi Wang, Zhuolun He, Chen Bai, Haoyu Yang, Bei Yu

An Adversarial Active Sampling-based Data Augmentation Framework for Manufacturable Chip Design

Mingjie Liu, Haoyu Yang, Zongyi Li, Kumara Sastry, Saumyadip Mukhopadhyay, Selim Dogru, Anima Anandkumar, David Z. Pan, Brucek Khailany, Haoxing (Mark) Ren

NeurIPS

LNS-Madam: Low-Precision Training in Logarithmic Number System Using Multiplicative Weight Update

Jiawei Zhao, Steve Dai, Rangharajan Venkatesan, Brian Zimmer, Mustafa Ali, Ming-Yu Liu, Brucek Khailany, William Dally, Anima Anandkumar

Why are Graph Neural Networks Effective for EDA Problems?

Haoxing (Mark) Ren, Siddhartha Nath, Yanqing Zhang, Hao Chen, Mingjie Liu

TransSizer: A Novel Transformer-Based Fast Gate Sizer

Siddhartha Nath, Geraldo Pradipta, Corey Hu, Tian Yang, Brucek Khailany, Haoxing (Mark) Ren

TAG: Learning Circuit Spatial Embedding from Layouts

Keren Zhu, Hao Chen, Walker Turner, George F. Kokai, Po-Hsuan Wei, David Z. Pan, Haoxing (Mark) Ren

Photonic Circuits for Accelerated Computing Systems

XT-PRAGGMA: Crosstalk Pessimism Reduction Accessible by GPU Gate-level Simulations and Machine Learning

Vidya Chhabria, Ben Keller, Yanqing Zhang, Sandeep Vollala, Sreedhar Patty, Haoxing (Mark) Ren, Brucek Khailany

Placement Optimization via PPA-Directed Graph Clustering

Yi-Chen Lu, Tian Yang, Sung Kyu Lim, Haoxing (Mark) Ren

From RTL to CUDA: A GPU Acceleration Flow for RTL Simulation with Batch Stimulus

Dian-Lun Lin, Haoxing (Mark) Ren, Yanqing Zhang, Brucek Khailany, Tsung-Wei Huang

A 0.297-pJ/bit 50.4-Gb/s/wire Inverter-Based Short-Reach Simultaneous Bidirectional Transceiver for Die-to-Die Interface in 5nm CMOS

Yoshinori Nishi, John W. Poulton, Xi Chen, Sanquan Song, Brian Zimmer, Walker Turner, Stephen Tell, Nikola Nedovic, John Wilson, William Dally, Tom Gray

A 17–95.6 TOPS/W Deep Learning Inference Accelerator with Per-Vector Scaled 4-bit Quantization for Transformers in 5nm

Ben Keller, Rangharajan Venkatesan, Steve Dai, Stephen Tell, Brian Zimmer, William Dally, Tom Gray, Brucek Khailany

Saving PAM4 Bus Energy with SMOREs: Sparse Multi-level Opportunistic Restricted Encodings

Mike O'Connor, Donghyuk Lee, Niladrish Chatterjee, Michael B. Sullivan, Steve Keckler

AutoCRAFT: Layout Automation for Custom Circuits in Advanced FinFET Technologies

Hao Chen, Walker Turner, Sanquan Song, Keren Zhu, George Kokai, Brian Zimmer, Tom Gray, Brucek Khailany, Haoxing (Mark) Ren

ISPD

Routability-Aware Placement for Advanced FinFET Analog Circuits with Satisfiability Modulo Theories

Hao Chen, Walker Turner, David Z. Pan, Haoxing (Mark) Ren

Generic Lithography Modeling with Dual-band Optics-Inspired Neural Networks

Haoyu Yang, Zongyi Li, Kumara Sastry, Saumyadip Mukhopadhyay, Mark Kilgard, Anima Anandkumar, Brucek Khailany, Vivek Singh, Haoxing (Mark) Ren

GATSPI: GPU Accelerated Gate-Level Simulation for Power Improvement

Yanqing Zhang, Haoxing (Mark) Ren, Akshay Sridharan, Brucek Khailany

Driving Down Link Energy and Driving Up Link Density in GPU Networks

DeePattern: Layout Pattern Generation with Transforming Convolutional Auto-Encoder

Haoyu Yang, Shuhe Li, Wen Chen, Piyush Pathak, Frank Gennari, Ya-Chieh Lai, Bei Yu

Best Paper Award

Machine Learning and Algorithms: Let Us Team Up for EDA

Haoxing (Mark) Ren, Brucek Khailany, Matt Fojtik, Yanqing Zhang

2020

NVCell: Generate Standard Cell Layout in Advanced Technology Nodes with Reinforcement Learning

Haoxing (Mark) Ren, Matt Fojtik, Brucek Khailany

How Software Can "Chip In" to the IC Design Process: A Multidisciplinary Approach May Attract New Talent and Accelerate Innovation

Alicia Klinefelter

Opportunities for RTL and Gate Level Simulation using GPUs

Yanqing Zhang, Haoxing (Mark) Ren, Brucek Khailany

Accelerating Chip Design with Machine Learning

Brucek Khailany, Haoxing (Mark) Ren, Steve Dai, Saad Godil, Ben Keller, Robert Kirby, Alicia Klinefelter, Rangharajan Venkatesan, Yanqing Zhang, Bryan Catanzaro, William Dally

ParaGraph: Layout Parasitics and Device Parameter Prediction using Graph Neural Networks

Haoxing (Mark) Ren, George Kokai, Walker Turner, Ting-Sheng Ku

GRANNITE: Graph Neural Network Inference for Transferable Power Estimation

Yanqing Zhang, Haoxing (Mark) Ren, Brucek Khailany

DREAMPlace: Deep Learning Toolkit-Enabled GPU Acceleration for Modern VLSI Placement

Yibo Lin, Zixuan Jiang, Jiaqi Gu, Wuxi Li, Shounak Dhar, Haoxing (Mark) Ren, Brucek Khailany, David Z. Pan

2021 IEEE Transactions on Computer-Aided Design Donald O. Pederson Best Paper Award

Reference-Noise Compensation Scheme for Single- Ended Package-to-Package Links

Xi Chen, Nikola Nedovic, Stephen Tell, Sudhir Kudva, Brian Zimmer, Trey Greer, John Poulton, Sanquan Song, Walker Turner, John Wilson, Tom Gray

ABCDPlace: Accelerated Batch-based Concurrent Detailed Placement on Multi-threaded CPUs and GPUs

Yibo Lin, Wuxi Li, Jiaqi Gu, Haoxing (Mark) Ren, Brucek Khailany, David Z. Pan

A 0.32–128 TOPS, Scalable Multi-Chip-Module-Based Deep Neural Network Inference Accelerator With Ground-Referenced Signaling in 16 nm

Brian Zimmer, Rangharajan Venkatesan, Yakun Sophia Shao, Jason Clemons, Matt Fojtik, Ted Jiang, Ben Keller, Alicia Klinefelter, Nathaniel Pinckney, Priyanka Raina, Stephen Tell, Yanqing Zhang, William Dally, Joel Emer, Tom Gray, Steve Keckler, Brucek Khailany

JSSC 2020 Best Paper award

FIST: A Feature-Importance Sampling and Tree-Based Method for Automatic Design Flow Parameter Tuning

Zhiyao Xie, Guan-Qi Fang, Yu-Hung Huang, Haoxing (Mark) Ren, Yanqing Zhang, Brucek Khailany, Shao-Yun Fang, Jiang Hu, Yiran Chen, Erick Carvajal Barboza

PowerNet: Transferable Dynamic IR Drop Estimation via Maximum Convolutional Neural Network

Zhiyao Xie, Haoxing (Mark) Ren, Brucek Khailany, Ye Sheng, Santosh Santosh, Jiang Hu, Yiran Chen