Angshuman Parashar

Dr. Angshuman Parashar joined NVIDIA in 2015 and is a member of the Architecture Research Group. His research focuses on building and evaluating architectures for spatial and data-parallel algorithms. Prior to NVIDIA, he was a member of the VSSAD group at Intel, where he worked with a small team of experts in architecture, languages, workloads and implementation to design and evaluate a new spatial architecture.

Parashar received his Ph.D. in Computer Science and Engineering from the Pennsylvania State University in 2007, and his B.Tech. in Computer Science and Engineering from the Indian Institute of Technology, Delhi in 2002.

List of publications

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Aamer Jaleel

Dr. Aamer Jaleel joined NVIDIA in 2015 and is a member of the Architecture Research Group (ARG). His research work focuses on cache and DRAM systems, workload scheduling, performance modeling, and workload characterization. Prior to joining NVIDIA, he was a Principal Engineer at Intel Massachusetts Inc. in the VSSAD research group. During his decade-long career at Intel, his research work contributed towards enhancement in performance modeling and cache hierarchy improvements of Intel’s next generation microprocessors. In the Fall of 2014, during his extended sabbatical from Intel, he also served as a Visiting Professor at the University of Minnesota, Minneapolis-St. Paul where he co-taught a graduate computer architecture course.

Jaleel received his Ph.D. in Electrical Engineering from the University of Maryland, College Park in 2006. He received his B.S. and M.S. in Computer Engineering also from the University of Maryland, College Park in 2000 and 2002 respectively. Jaleel has co-authored more than a dozen patents and over 30 technical publications.

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Tim Foley

Tim joined NVIDIA in 2015, and pursues research on programming models, languages, and APIs for real-time graphics and games.

Tim has previously contributed to languages and compilers for computing on GPUs, GPU-accellerated ray tracing, and novel shading languages for real-time graphics. Tim received a Ph.D. in Computer Science from Stanford in 2012.

Cris Cecka


Dr. Cris Cecka joined NVIDIA Research in 2015 to deploy his interests in developing advanced numerical algorithms and software. Previously, Cris worked at the new Institute for Applied Computational Science at Harvard University as a research scientist and lecturer, where he developed courses on parallel computing and robust software development in scientific computing. He also worked in the Mathematics Department at the Massachusetts Institute of Technology as a research associate, where he focused on developing and applying integral equation methods and generalized N-body problems via hierarchical matrix factorizations. He received his Ph.D. from Stanford University in computational and mathematical engineering in 2011.


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Turner Whitted

Turner Whitted joined NVIDIA in 2014 after 15 years at Microsoft Research where he founded the hardware devices group and managed the graphics group along with a variety of other groups devoted to HCI. He was a co-inventor of the signal processing algorithm for ClearTypeTM. He co-founded Numerical Design Limited in 1983 and served as president and technical director until 1996. Earlier, as a member of the technical staff at Bell Laboratories, he introduced recursive ray tracing as an implementation of global illumination. In his early career he designed digital test equipment, antenna measurement systems, and components of a sonar signal processor.

He earned BSE and MS degrees from Duke University and a PhD from North Carolina State University, all in electrical engineering. He is an adjunct research professor of Computer Science at the University of North Carolina and adjunct professor of Electrical and Computer Engineering at North Carolina State University. In the past he has served on the editorial boards of IEEE Computer Graphics and Applications and ACM Transactions on Graphics, was papers chair for SIGGRAPH 97, and served on the SIGGRAPH executive committee. He is an ACM Fellow and a member of the National Academy of Engineering

Rangharajan Venkatesan

Rangharajan Venkatesan is a Senior Research Scientist in the ASIC & VLSI Research group in NVIDIA. He received the B.Tech. degree in Electronics and Communication Engineering from the Indian Institute of Technology,  Roorkee in 2009 and the Ph.D. degree in Electrical and Computer Engineering from Purdue University in August 2014. His research interests include variation-tolerant design methodologies, low power SoC design, machine learning, spintronic memories, and approximate computing. During his Ph.D., he was a recipient of Purdue’s Ross Fellowship for the year 2009–2010 and the Bilsland Dissertation Fellowship for the year 2013–2014.  His work on spintronic memory design was recognized with the Best Paper Award at the International Symposium on Low Power Electronics and Design (ISLPED), 2012 and Best paper nomination at the Design, Automation and Test in Europe (DATE), 2017.



Mike Bauer

Michael Bauer joined NVIDIA Research in October of 2014 after finishing his PhD in computer science at Stanford University.  As part of his thesis, he developed the Legion programming system for high performance supercomputing codes.  Legion is currently deployed in several production applications running on the top supercomputers in the world.  Michael was also the primary author of both the CudaDMA library and Singe DSL compiler, both of which were early examples of warp-specialized GPU programming.


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