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Circuits and VLSI Design

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Circuits and VLSI Design

2022

TransSizer: A Novel Transformer-Based Fast Gate Sizer

Siddhartha Nath, Geraldo Pradipta, Corey Hu, Tian Yang, Brucek Khailany, Haoxing (Mark) Ren

TAG: Learning Circuit Spatial Embedding from Layouts

Keren Zhu, Hao Chen, Walker Turner, George F. Kokai, Po-Hsuan Wei, David Z. Pan, Haoxing (Mark) Ren

Photonic Circuits for Accelerated Computing Systems

XT-PRAGGMA: Crosstalk Pessimism Reduction Accessible by GPU Gate-level Simulations and Machine Learning

Vidya Chhabria, Ben Keller, Yanqing Zhang, Sandeep Vollala, Sreedhar Patty, Haoxing (Mark) Ren, Brucek Khailany

Placement Optimization via PPA-Directed Graph Clustering

Yi-Chen Lu, Tian Yang, Sung Kyu Lim, Haoxing (Mark) Ren

From RTL to CUDA: A GPU Acceleration Flow for RTL Simulation with Batch Stimulus

Dian-Lun Lin, Haoxing (Mark) Ren, Yanqing Zhang, Brucek Khailany, Tsung-Wei Huang

A 0.297-pJ/bit 50.4-Gb/s/wire Inverter-Based Short-Reach Simultaneous Bidirectional Transceiver for Die-to-Die Interface in 5nm CMOS

Yoshinori Nishi, John W. Poulton, Xi Chen, Sanquan Song, Brian Zimmer, Walker Turner, Stephen Tell, Nikola Nedovic, John Wilson, William Dally, Tom Gray

A 17–95.6 TOPS/W Deep Learning Inference Accelerator with Per-Vector Scaled 4-bit Quantization for Transformers in 5nm

Ben Keller, Rangharajan Venkatesan, Steve Dai, Stephen Tell, Brian Zimmer, William Dally, Tom Gray, Brucek Khailany

Saving PAM4 Bus Energy with SMOREs: Sparse Multi-level Opportunistic Restricted Encodings

Mike O'Connor, Donghyuk Lee, Niladrish Chatterjee, Michael B. Sullivan, Steve Keckler

AutoCRAFT: Layout Automation for Custom Circuits in Advanced FinFET Technologies

Hao Chen, Walker Turner, Sanquan Song, Keren Zhu, George Kokai, Brian Zimmer, Tom Gray, Brucek Khailany, Haoxing (Mark) Ren

ISPD

Routability-Aware Placement for Advanced FinFET Analog Circuits with Satisfiability Modulo Theories

Hao Chen, Walker Turner, David Z. Pan, Haoxing (Mark) Ren

Generic Lithography Modeling with Dual-band Optics-Inspired Neural Networks

Haoyu Yang, Zongyi Li, Kumara Sastry, Saumyadip Mukhopadhyay, Mark Kilgard, Anima Anandkumar, Brucek Khailany, Vivek Singh, Haoxing (Mark) Ren

GATSPI: GPU Accelerated Gate-Level Simulation for Power Improvement

Yanqing Zhang, Haoxing (Mark) Ren, Akshay Sridharan, Brucek Khailany

Driving Down Link Energy and Driving Up Link Density in GPU Networks

DeePattern: Layout Pattern Generation with Transforming Convolutional Auto-Encoder

Haoyu Yang, Shuhe Li, Wen Chen, Piyush Pathak, Frank Gennari, Ya-Chieh Lai, Bei Yu

Best Paper Award

Machine Learning and Algorithms: Let Us Team Up for EDA

Haoxing (Mark) Ren, Brucek Khailany, Matt Fojtik, Yanqing Zhang

2021

NVCell: Standard Cell Layout in Advanced Technology Nodes with Reinforcement Learning

Haoxing (Mark) Ren, Matt Fojtik, Brucek Khailany

Softermax: Hardware/Software Co-Design of an Efficient Softmax for Transformers

Jacob R. Stevens, Rangharajan Venkatesan, Steve Dai, Brucek Khailany, Anand Raghunathan

IPA: Floorplan-Aware SystemC Interconnect Performance Modeling and Generation for HLS-based SoCs

Nathaniel Pinckney, Rangharajan Venkatesan, Ben Keller, Brucek Khailany

Graph Learning-Based Arithmetic Block Identification

Zhuolun He, Ziyi Wang, Chen Bai, Haoyu Yang, Bei Yu

Simba: scaling deep-learning inference with chiplet-based architecture

Yakun Sophia Shao, Jason Clemons, Rangharajan Venkatesan, Brian Zimmer, Matt Fojtik, Ted Jiang, Ben Keller, Alicia Klinefelter, Nathaniel Pinckney, Priyanka Raina, Stephen Tell, Yanqing Zhang, William Dally, Joel Emer, Tom Gray, Brucek Khailany, Steve Keckler

ACM Research Highlight

VS-QUANT: Per-Vector Scaled Quantization for Accurate Low-Precision Neural Network Inference

Steve Dai, Rangharajan Venkatesan, Haoxing (Mark) Ren, Brian Zimmer, William Dally, Brucek Khailany

Fair and Comprehensive Benchmarking of Machine Learning Processing Chips

Geoffrey W. Burr, SukHwan Lim, Boris Murmann, Rangharajan Venkatesan, Marian Verhelst

Verifying High-Level Latency-Insensitive Designs with Formal Model Checking

Steve Dai, Alicia Klinefelter, Haoxing (Mark) Ren, Rangharajan Venkatesan, Ben Keller, Nathaniel Pinckney, Brucek Khailany

Ground-Referenced Single-Ended Signaling: Applications for High-Density Short-Haul Communication Systems

John Wilson, Walker Turner, John Poulton

Parasitic-Aware Analog Circuit Sizing with Graph Neural Networks and Bayesian Optimization

Mingjie Liu, Walker Turner, George Kokai, David Z. Pan, Brucek Khailany, Haoxing (Mark) Ren

MAVIREC: ML-Aided Vectored IR-Drop Estimation and Classification

Vidya A. Chhabria, Yanqing Zhang, Haoxing (Mark) Ren, Ben Keller, Brucek Khailany, Sachin S. Sapatnekar

Standard Cell Routing with Reinforcement Learning and Genetic Algorithm in Advanced Technology Nodes

Haoxing (Mark) Ren, Matt Fojtik

2020

NVCell: Generate Standard Cell Layout in Advanced Technology Nodes with Reinforcement Learning

Haoxing (Mark) Ren, Matt Fojtik, Brucek Khailany

How Software Can "Chip In" to the IC Design Process: A Multidisciplinary Approach May Attract New Talent and Accelerate Innovation

Alicia Klinefelter

Opportunities for RTL and Gate Level Simulation using GPUs

Yanqing Zhang, Haoxing (Mark) Ren, Brucek Khailany

Accelerating Chip Design with Machine Learning

Brucek Khailany, Haoxing (Mark) Ren, Steve Dai, Saad Godil, Ben Keller, Robert Kirby, Alicia Klinefelter, Rangharajan Venkatesan, Yanqing Zhang, Bryan Catanzaro, William Dally