Publications

Our publications provide insight into some of our leading-edge research.

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2023

CircuitOps: An ML Infrastructure Enabling Generative AI for VLSI Circuit Optimization
Rongjian Liang, Anthony Agnesina, Geraldo Pradipta, Vidya A. Chhabria, Haoxing (Mark) Ren
ChipNeMo: Domain-Adapted LLMs for Chip Design
Mingjie Liu, Teo Ene, Robert Kirby, Chris Cheng, Nathaniel Pinckney, Rongjian Liang, Jonah Alben, Himyanshu Anand, Sanmitra Banerjee, Ismet Bayraktaroglu, Bonita Bhaskaran, Bryan Catanzaro, Arjun Chaudhuri, Sharon Clay, Bill Dally, Laura Dang, Parikshit Deshpande, Siddhanth Dhodhi, Sameer Halepete, Eric Hill, Jiashang Hu, Sumit Jain, Brucek Khailany, George Kokai, Kishor Kunal, Xiaowei Li, Charley Lind, Hao Liu, Stuart Oberman, Sujeet Omar, Sreedhar Pratty, Jonathan Raman, Ambar Sarkar, Zhengjiang Shao, Hanfei Sun, Pratik P Suthar, Varun Tej, Walker Turner, Kaizhe Xu, Haoxing (Mark) Ren
VerilogEval: Evaluating Large Language Models for Verilog Code Generation
Mingjie Liu, Nathaniel Pinckney, Brucek Khailany, Haoxing (Mark) Ren
Late Breaking Results: Test Selection For RTL Coverage By Unsupervised Learning From Fast Functional Simulation
Rongjian Liang, Nathaniel Pinckney, Yuji Chai, Haoxing (Mark) Ren, Brucek Khailany
Efficient Transformer Inference with Statically Structured Sparse Attention
Steve Dai, Hasan Genc, Rangharajan Venkatesan, Brucek Khailany
Physics-Informed Optical Kernel Regression Using Complex-valued Neural Fields
Guojin Chen, Zehua Pei, Haoyu Yang, Yuzhe Ma, Bei Yu, Martin Wong
A 0.190-pJ/bit 25.2-Gb/s/wire Inverter-Based AC-Coupled Transceiver for Short-Reach Die-to-Die Interfaces in 5-nm CMOS
Yoshinori Nishi, John W. Poulton, Xi Chen, Sanquan Song, Brian Zimmer, Walker Turner, Stephen Tell, Nikola Nedovic, John Wilson, William Dally, Tom Gray
A 9.7fJ/Conv.-Step Capacitive Sensor Readout Circuit with Incremental Zoomed Time Domain Quantization
Zilong Shen, Xiyuan Tang, Zhongyi Wu, Haoyang Luo, Zongnan Wang, Mingjie Liu, Xing Zhang, Yuan Wang
A 0.297-pJ/Bit 50.4-Gb/s/Wire Inverter-Based Short-Reach Simultaneous Bi-Directional Transceiver for Die-to-Die Interface in 5-nm CMOS
Yoshinori Nishi, John W. Poulton, Walker Turner, Xi Chen, Sanquan Song, Brian Zimmer, Stephen Tell, Nikola Nedovic, John Wilson, William Dally, Tom Gray
Reinforcement Learning Guided Detailed Routing for Custom Circuits
Hao Chen, Kai-Chieh Hsu, Walker Turner, Po-Hsuan Wei, Keren Zhu, David Z. Pan, Haoxing (Mark) Ren
DREAM-GAN: Advancing DREAMPlace towards Commercial-Quality using Generative Adversarial Learning
Yi-Chen Lu, Haoxing (Mark) Ren, Hao-Hsiang Hsiao, Sung Kyu Lim
NVCell 2: Routability-Driven Standard Cell Layout in Advanced Nodes with Lattice Graph Routability Model
Chia-Tung (Mark) Ho, Alvin Ho, Matt Fojtik, Minsoo Kim, Shang Wei, Yaguang LI, Brucek Khailany, Haoxing (Mark) Ren
AutoDMP: Automated DREAMPlace-based Macro Placement
Anthony Agnesina, Puranjay Rajvanshi, Tian Yang, Geraldo Pradipta, Austin Jiao, Ben Keller, Brucek Khailany, Haoxing (Mark) Ren
On Legalization of Die Bonding Bumps and Pads for 3D ICs
Sai Pentapati, Anthony Agnesina, Moritz Brunion, Yen-Hsiang Huang, Sung Kyu Lim
Enabling Scalable AI Computational Lithography with Physics-Inspired Models
Haoyu Yang, Haoxing (Mark) Ren
Beyond CPO: A Motivation and Approach for Bringing Optics onto the Silicon Interposer
Ben Lee, Nikola Nedovic, Trey Greer, Tom Gray
A 95.6-TOPS/W Deep Learning Inference Accelerator With Per-Vector Scaled 4-bit Quantization in 5 nm
Ben Keller, Rangharajan Venkatesan, Steve Dai, Stephen Tell, Brian Zimmer, Charbel Sakr, William Dally, Tom Gray, Brucek Khailany
BufFormer: A Generative ML Framework for Scalable Buffering
Rongjian Liang, Siddhartha Nath, Anand Rajaram, Jiang Hu, Haoxing (Mark) Ren

2021

NVCell: Standard Cell Layout in Advanced Technology Nodes with Reinforcement Learning
Haoxing (Mark) Ren, Matt Fojtik, Brucek Khailany
Softermax: Hardware/Software Co-Design of an Efficient Softmax for Transformers
Jacob R. Stevens, Rangharajan Venkatesan, Steve Dai, Brucek Khailany, Anand Raghunathan
IPA: Floorplan-Aware SystemC Interconnect Performance Modeling and Generation for HLS-based SoCs
Nathaniel Pinckney, Rangharajan Venkatesan, Ben Keller, Brucek Khailany
Graph Learning-Based Arithmetic Block Identification
Zhuolun He, Ziyi Wang, Chen Bai, Haoyu Yang, Bei Yu
Simba: scaling deep-learning inference with chiplet-based architecture
Yakun Sophia Shao, Jason Clemons, Rangharajan Venkatesan, Brian Zimmer, Matt Fojtik, Ted Jiang, Ben Keller, Alicia Klinefelter, Nathaniel Pinckney, Priyanka Raina, Stephen Tell, Yanqing Zhang, William Dally, Joel Emer, Tom Gray, Brucek Khailany, Steve Keckler
ACM Research Highlight
VS-QUANT: Per-Vector Scaled Quantization for Accurate Low-Precision Neural Network Inference
Steve Dai, Rangharajan Venkatesan, Haoxing (Mark) Ren, Brian Zimmer, William Dally, Brucek Khailany
Fair and Comprehensive Benchmarking of Machine Learning Processing Chips
Geoffrey W. Burr, SukHwan Lim, Boris Murmann, Rangharajan Venkatesan, Marian Verhelst
Verifying High-Level Latency-Insensitive Designs with Formal Model Checking
Steve Dai, Alicia Klinefelter, Haoxing (Mark) Ren, Rangharajan Venkatesan, Ben Keller, Nathaniel Pinckney, Brucek Khailany
Ground-Referenced Single-Ended Signaling: Applications for High-Density Short-Haul Communication Systems
John Wilson, Walker Turner, John Poulton
Parasitic-Aware Analog Circuit Sizing with Graph Neural Networks and Bayesian Optimization
Mingjie Liu, Walker Turner, George Kokai, David Z. Pan, Brucek Khailany, Haoxing (Mark) Ren
MAVIREC: ML-Aided Vectored IR-Drop Estimation and Classification
Vidya A. Chhabria, Yanqing Zhang, Haoxing (Mark) Ren, Ben Keller, Brucek Khailany, Sachin S. Sapatnekar
Standard Cell Routing with Reinforcement Learning and Genetic Algorithm in Advanced Technology Nodes
Haoxing (Mark) Ren, Matt Fojtik